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[/] [or1k/] [tags/] [stable_0_2_0_rc2/] - Rev 996

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Rev Log message Author Age Path
996 some minor bugs fixed markom 8026d 05h /or1k/tags/stable_0_2_0_rc2
994 Store buffer has been tested and it works. BY default it is still disabled until uClinux confirms correct operation on FPGA board. lampret 8026d 13h /or1k/tags/stable_0_2_0_rc2
993 Fixed IMMU bug. lampret 8026d 13h /or1k/tags/stable_0_2_0_rc2
992 A bug when cache enabled and bus error comes fixed. simons 8026d 22h /or1k/tags/stable_0_2_0_rc2
991 Different memory controller. simons 8026d 22h /or1k/tags/stable_0_2_0_rc2
990 Test is now complete. simons 8026d 22h /or1k/tags/stable_0_2_0_rc2
989 c++ is making problems so, for now, it is excluded. simons 8028d 06h /or1k/tags/stable_0_2_0_rc2
988 ORP architecture supported. simons 8028d 22h /or1k/tags/stable_0_2_0_rc2
987 ORP architecture supported. simons 8029d 05h /or1k/tags/stable_0_2_0_rc2
986 outputs out of function are not registered anymore markom 8029d 06h /or1k/tags/stable_0_2_0_rc2
985 DTLB translation doesn't work on or1ksim when IC/DC enabled. lampret 8029d 17h /or1k/tags/stable_0_2_0_rc2
984 Disable SB until it is tested lampret 8029d 17h /or1k/tags/stable_0_2_0_rc2
983 First checkin lampret 8029d 19h /or1k/tags/stable_0_2_0_rc2
982 Moved to sim/bin lampret 8029d 19h /or1k/tags/stable_0_2_0_rc2
981 First checkin. lampret 8029d 19h /or1k/tags/stable_0_2_0_rc2
980 Removed sim.tcl that shouldn't be here. lampret 8029d 19h /or1k/tags/stable_0_2_0_rc2
979 Removed old test case binaries. lampret 8029d 20h /or1k/tags/stable_0_2_0_rc2
978 Added variable delay for SRAM. lampret 8029d 20h /or1k/tags/stable_0_2_0_rc2
977 Added store buffer. lampret 8029d 20h /or1k/tags/stable_0_2_0_rc2
976 Added store buffer lampret 8029d 20h /or1k/tags/stable_0_2_0_rc2

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