OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [tags/] [stable_0_2_0_rc2] - Rev 616

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
616 flags test added markom 8205d 06h /or1k/tags/stable_0_2_0_rc2
615 cmov and extxx instructions; add, addi, and, andi now set flag markom 8205d 06h /or1k/tags/stable_0_2_0_rc2
614 Changed to support new debug if. simons 8205d 13h /or1k/tags/stable_0_2_0_rc2
613 init: trap exception occurs always; initialization of sr not needed anymore markom 8206d 10h /or1k/tags/stable_0_2_0_rc2
612 Tick timer period extended to meet real timing. simons 8206d 11h /or1k/tags/stable_0_2_0_rc2
611 EEAR register is not changed by trap, sys, int, tick and range exception. simons 8207d 13h /or1k/tags/stable_0_2_0_rc2
610 Changed default reset values for SR and ESR to match or1ksim's. Fixed flop model in or1200_dpram_32x32 when OR1200_XILINX_RAM32X1D is defined. lampret 8207d 13h /or1k/tags/stable_0_2_0_rc2
609 Added wb_err_o to flash and sram i/f for testing the buserr exception. lampret 8207d 13h /or1k/tags/stable_0_2_0_rc2
608 Range exception removed from test. simons 8208d 08h /or1k/tags/stable_0_2_0_rc2
607 single step steps just one instruction ^c bug fixed markom 8208d 08h /or1k/tags/stable_0_2_0_rc2
606 raw register range bug fixed; acv_uart test passes markom 8209d 09h /or1k/tags/stable_0_2_0_rc2
605 simulator prints out a message, when gdb is not attached and stall occurs; OV flag fixed markom 8209d 09h /or1k/tags/stable_0_2_0_rc2
604 mul test repaired - signed multiplication; obsolete pic test removed; make check pass markom 8209d 09h /or1k/tags/stable_0_2_0_rc2
603 fixed bfd markom 8209d 11h /or1k/tags/stable_0_2_0_rc2
602 Renamed targets. Switched off debug. lampret 8210d 10h /or1k/tags/stable_0_2_0_rc2
601 or1k has anly one external interrupt exception. Tick timer exception added. simons 8210d 21h /or1k/tags/stable_0_2_0_rc2
600 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8210d 22h /or1k/tags/stable_0_2_0_rc2
599 No more low/high priority interrupts (PICPR removed). Added tick timer exception. simons 8210d 22h /or1k/tags/stable_0_2_0_rc2
598 Fixed SR[EXR] (this is now actually SR[TEE]) lampret 8211d 07h /or1k/tags/stable_0_2_0_rc2
597 Fixed OR1200_XILINX_RAM32X1D. lampret 8211d 07h /or1k/tags/stable_0_2_0_rc2

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.