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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 88

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Rev	Log message	Author	Age	Path
88	Added the reset value parameter to the synchronizer flop module. Added resets to all synchronizer flop instances. Repaired initial sync value in fifos.	mihad	7794d 09h	/pci/tags/asyst_2/rtl/verilog
86	Entered the option to disable no response counter in wb master.	mihad	7806d 07h	/pci/tags/asyst_2/rtl/verilog
83	Cleaned up the code. No functional changes.	mihad	7835d 04h	/pci/tags/asyst_2/rtl/verilog
81	Updated synchronization in top level fifo modules.	mihad	7849d 01h	/pci/tags/asyst_2/rtl/verilog
79	Updated.	mihad	7852d 06h	/pci/tags/asyst_2/rtl/verilog
78	Old files with wrong names removed.	mihad	7852d 06h	/pci/tags/asyst_2/rtl/verilog
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7852d 06h	/pci/tags/asyst_2/rtl/verilog
73	Bug fixes, testcases added.	mihad	7858d 06h	/pci/tags/asyst_2/rtl/verilog
72	* empty log message *	mihad	7905d 10h	/pci/tags/asyst_2/rtl/verilog
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7913d 02h	/pci/tags/asyst_2/rtl/verilog
69	Changed BIST signal names etc..	mihad	7950d 10h	/pci/tags/asyst_2/rtl/verilog
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7953d 19h	/pci/tags/asyst_2/rtl/verilog
67	Changed BIST signals for RAMs.	tadejm	7954d 00h	/pci/tags/asyst_2/rtl/verilog
66	Changed empty status generation in pciw_fifo_control.v	mihad	7957d 10h	/pci/tags/asyst_2/rtl/verilog
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7960d 08h	/pci/tags/asyst_2/rtl/verilog
63	Added additional testcase and changed rst name in BIST to trst	mihad	7960d 12h	/pci/tags/asyst_2/rtl/verilog
62	Added BIST signals for RAMs.	mihad	7963d 05h	/pci/tags/asyst_2/rtl/verilog
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7971d 05h	/pci/tags/asyst_2/rtl/verilog
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7971d 07h	/pci/tags/asyst_2/rtl/verilog
58	Removed all logic from asynchronous reset network	mihad	7976d 07h	/pci/tags/asyst_2/rtl/verilog

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[/] [pci/] [tags/] [asyst_2/] [rtl/] [verilog/] - Rev 88

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