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[/] [pci/] [tags/] [asyst_3/] - Rev 73

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Rev Log message Author Age Path
73 Bug fixes, testcases added. mihad 7877d 19h /pci/tags/asyst_3
72 *** empty log message *** mihad 7924d 23h /pci/tags/asyst_3
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7932d 15h /pci/tags/asyst_3
69 Changed BIST signal names etc.. mihad 7969d 22h /pci/tags/asyst_3
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7973d 08h /pci/tags/asyst_3
67 Changed BIST signals for RAMs. tadejm 7973d 13h /pci/tags/asyst_3
66 Changed empty status generation in pciw_fifo_control.v mihad 7976d 23h /pci/tags/asyst_3
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7979d 21h /pci/tags/asyst_3
64 The testcase I just added in previous revision repaired mihad 7979d 23h /pci/tags/asyst_3
63 Added additional testcase and changed rst name in BIST to trst mihad 7980d 01h /pci/tags/asyst_3
62 Added BIST signals for RAMs. mihad 7982d 18h /pci/tags/asyst_3
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7990d 18h /pci/tags/asyst_3
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 19h /pci/tags/asyst_3
58 Removed all logic from asynchronous reset network mihad 7995d 20h /pci/tags/asyst_3
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7996d 01h /pci/tags/asyst_3
56 Number of state bits define was removed mihad 7996d 16h /pci/tags/asyst_3
55 Changed state machine encoding to true one-hot mihad 7996d 17h /pci/tags/asyst_3
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8029d 18h /pci/tags/asyst_3
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8029d 22h /pci/tags/asyst_3
52 Oops, never before noticed that OC header is missing mihad 8030d 02h /pci/tags/asyst_3

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