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[/] [pci/] [tags/] [rel_10] - Rev 83

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Rev Log message Author Age Path
83 Cleaned up the code. No functional changes. mihad 7823d 23h /pci/tags/rel_10
81 Updated synchronization in top level fifo modules. mihad 7837d 19h /pci/tags/rel_10
79 Updated. mihad 7841d 00h /pci/tags/rel_10
78 Old files with wrong names removed. mihad 7841d 01h /pci/tags/rel_10
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7841d 01h /pci/tags/rel_10
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7844d 00h /pci/tags/rel_10
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7847d 01h /pci/tags/rel_10
73 Bug fixes, testcases added. mihad 7847d 01h /pci/tags/rel_10
72 *** empty log message *** mihad 7894d 05h /pci/tags/rel_10
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7901d 21h /pci/tags/rel_10
69 Changed BIST signal names etc.. mihad 7939d 04h /pci/tags/rel_10
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7942d 14h /pci/tags/rel_10
67 Changed BIST signals for RAMs. tadejm 7942d 19h /pci/tags/rel_10
66 Changed empty status generation in pciw_fifo_control.v mihad 7946d 05h /pci/tags/rel_10
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7949d 03h /pci/tags/rel_10
64 The testcase I just added in previous revision repaired mihad 7949d 05h /pci/tags/rel_10
63 Added additional testcase and changed rst name in BIST to trst mihad 7949d 07h /pci/tags/rel_10
62 Added BIST signals for RAMs. mihad 7952d 00h /pci/tags/rel_10
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7960d 00h /pci/tags/rel_10
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7960d 01h /pci/tags/rel_10

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