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[/] [pci/] [tags/] [rel_10] - Rev 97

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Rev Log message Author Age Path
97 Doing a little bit of cleanup. mihad 7705d 04h /pci/tags/rel_10
96 Update! mihad 7705d 05h /pci/tags/rel_10
95 Removed this file, because it was too large - long download time. mihad 7705d 05h /pci/tags/rel_10
94 Changed one critical PCI bus signal logic. mihad 7705d 05h /pci/tags/rel_10
93 Added a test application! mihad 7705d 12h /pci/tags/rel_10
92 Update! mihad 7705d 12h /pci/tags/rel_10
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7741d 02h /pci/tags/rel_10
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7741d 02h /pci/tags/rel_10
89 Burst 2 error fixed. mihad 7777d 03h /pci/tags/rel_10
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7783d 02h /pci/tags/rel_10
87 Updated acording to RTL changes. mihad 7794d 23h /pci/tags/rel_10
86 Entered the option to disable no response counter in wb master. mihad 7794d 23h /pci/tags/rel_10
85 Changed Vendor ID defines. mihad 7795d 04h /pci/tags/rel_10
84 Changed vendor ID. mihad 7798d 22h /pci/tags/rel_10
83 Cleaned up the code. No functional changes. mihad 7823d 20h /pci/tags/rel_10
81 Updated synchronization in top level fifo modules. mihad 7837d 17h /pci/tags/rel_10
79 Updated. mihad 7840d 22h /pci/tags/rel_10
78 Old files with wrong names removed. mihad 7840d 22h /pci/tags/rel_10
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7840d 22h /pci/tags/rel_10
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7843d 22h /pci/tags/rel_10

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