OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_11/] - Rev 154

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
154 New directory structure. root 5553d 12h /pci/tags/rel_11
127 This commit was manufactured by cvs2svn to create tag 'rel_11'. 7479d 04h /tags/rel_11
126 ifdef - endif statements put in separate lines for flint compatibility. simons 7479d 04h /trunk
124 Added missing signals to 2 sensitivity lists. Everything works the same as before. tadejm 7517d 11h /trunk
122 mbist signals updated according to newest convention markom 7524d 11h /trunk
119 Added support for WB B3. Some testcases were updated. tadejm 7580d 23h /trunk
118 Some minor changes due to changes in core. tadejm 7580d 23h /trunk
117 WB Master is now WISHBONE B3 compatible. tadejm 7580d 23h /trunk
116 Corrected bug when writing to FIFO (now it is registered). tadejm 7580d 23h /trunk
115 Added signals for WB Master B3. tadejm 7580d 23h /trunk
113 ifdefs moved to thier own lines, this confuses some of the tools. simons 7588d 02h /trunk
111 synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated. simons 7588d 07h /trunk
110 Module that converts slave WISHBONE B3 accesses to
WISHBONE B2 accesses with CAB.
mihad 7590d 06h /trunk
109 There was missing path to hdl.var file. tadejm 7594d 04h /trunk
108 Added 'three_left_out' to pci_pciw_fifo signaling three locations before full. Added comparison between current registered cbe and next unregistered cbe to signal wb_master whether it is allowed to performe burst or not. Due to this, I needed 'three_left_out' so that writing to pci_pciw_fifo can be registered, otherwise timing problems would occure. tadejm 7594d 04h /trunk
107 Added status when checking disconnect with or without data. Before it was only retry, now there is stop and retry. tadejm 7594d 04h /trunk
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.
mihad 7599d 02h /trunk
105 Wrong pci_bridge32.v file included in the project! mihad 7604d 09h /trunk
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.
mihad 7604d 12h /trunk
103 Added test application and modified files to support it. mihad 7651d 09h /trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.