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[/] [pci/] [tags/] [rel_11/] [apps/] - Rev 98

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Rev Log message Author Age Path
98 Cleanup. mihad 7720d 02h /pci/tags/rel_11/apps
97 Doing a little bit of cleanup. mihad 7720d 02h /pci/tags/rel_11/apps
96 Update! mihad 7720d 02h /pci/tags/rel_11/apps
93 Added a test application! mihad 7720d 09h /pci/tags/rel_11/apps
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7756d 00h /pci/tags/rel_11/apps
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7756d 00h /pci/tags/rel_11/apps
85 Changed Vendor ID defines. mihad 7810d 01h /pci/tags/rel_11/apps
84 Changed vendor ID. mihad 7813d 19h /pci/tags/rel_11/apps
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7855d 19h /pci/tags/rel_11/apps
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7858d 19h /pci/tags/rel_11/apps
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7861d 20h /pci/tags/rel_11/apps
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7974d 20h /pci/tags/rel_11/apps
38 This file is not needed tadej 8113d 20h /pci/tags/rel_11/apps
36 *** empty log message *** tadej 8113d 21h /pci/tags/rel_11/apps
31 User defined constants used for Test Application tadej 8194d 16h /pci/tags/rel_11/apps
29 Xilinx synthesys log file tadej 8195d 03h /pci/tags/rel_11/apps
25 *** empty log message *** mihad 8215d 18h /pci/tags/rel_11/apps
21 Repaired a few bugs, updated specification, added test bench files and design document mihad 8215d 21h /pci/tags/rel_11/apps
14 *** empty log message *** mihad 8215d 23h /pci/tags/rel_11/apps
5 Added .o file for kernel 2.4.3 mihad 8337d 19h /pci/tags/rel_11/apps

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