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[/] [pci/] [tags/] [rel_12/] - Rev 76

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Rev Log message Author Age Path
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7827d 18h /pci/tags/rel_12
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7830d 19h /pci/tags/rel_12
73 Bug fixes, testcases added. mihad 7830d 19h /pci/tags/rel_12
72 *** empty log message *** mihad 7877d 23h /pci/tags/rel_12
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7885d 15h /pci/tags/rel_12
69 Changed BIST signal names etc.. mihad 7922d 22h /pci/tags/rel_12
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7926d 08h /pci/tags/rel_12
67 Changed BIST signals for RAMs. tadejm 7926d 12h /pci/tags/rel_12
66 Changed empty status generation in pciw_fifo_control.v mihad 7929d 23h /pci/tags/rel_12
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7932d 21h /pci/tags/rel_12
64 The testcase I just added in previous revision repaired mihad 7932d 23h /pci/tags/rel_12
63 Added additional testcase and changed rst name in BIST to trst mihad 7933d 01h /pci/tags/rel_12
62 Added BIST signals for RAMs. mihad 7935d 18h /pci/tags/rel_12
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7943d 18h /pci/tags/rel_12
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7943d 19h /pci/tags/rel_12
58 Removed all logic from asynchronous reset network mihad 7948d 19h /pci/tags/rel_12
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7949d 01h /pci/tags/rel_12
56 Number of state bits define was removed mihad 7949d 16h /pci/tags/rel_12
55 Changed state machine encoding to true one-hot mihad 7949d 17h /pci/tags/rel_12
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7982d 18h /pci/tags/rel_12

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