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[/] [pci/] [tags/] [rel_12/] [sim/] - Rev 118

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Rev Log message Author Age Path
118 Some minor changes due to changes in core. tadejm 7656d 22h /pci/tags/rel_12/sim
109 There was missing path to hdl.var file. tadejm 7670d 02h /pci/tags/rel_12/sim
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7675d 00h /pci/tags/rel_12/sim
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7680d 10h /pci/tags/rel_12/sim
95 Removed this file, because it was too large - long download time. mihad 7727d 08h /pci/tags/rel_12/sim
92 Update! mihad 7727d 16h /pci/tags/rel_12/sim
81 Updated synchronization in top level fifo modules. mihad 7859d 20h /pci/tags/rel_12/sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7863d 02h /pci/tags/rel_12/sim
73 Bug fixes, testcases added. mihad 7869d 02h /pci/tags/rel_12/sim
72 *** empty log message *** mihad 7916d 06h /pci/tags/rel_12/sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7971d 08h /pci/tags/rel_12/sim
62 Added BIST signals for RAMs. mihad 7974d 01h /pci/tags/rel_12/sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7982d 01h /pci/tags/rel_12/sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7982d 02h /pci/tags/rel_12/sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8021d 09h /pci/tags/rel_12/sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8024d 02h /pci/tags/rel_12/sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8030d 07h /pci/tags/rel_12/sim
42 Removed out of date files mihad 8042d 08h /pci/tags/rel_12/sim
30 Example of PCI testbench log file mihad 8202d 06h /pci/tags/rel_12/sim
27 Modified testbench and fixed some bugs mihad 8205d 01h /pci/tags/rel_12/sim

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