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[/] [pci/] [tags/] [rel_12/] [sim/] - Rev 92

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Rev Log message Author Age Path
92 Update! mihad 7724d 05h /pci/tags/rel_12/sim
81 Updated synchronization in top level fifo modules. mihad 7856d 09h /pci/tags/rel_12/sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7859d 14h /pci/tags/rel_12/sim
73 Bug fixes, testcases added. mihad 7865d 15h /pci/tags/rel_12/sim
72 *** empty log message *** mihad 7912d 19h /pci/tags/rel_12/sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7967d 21h /pci/tags/rel_12/sim
62 Added BIST signals for RAMs. mihad 7970d 14h /pci/tags/rel_12/sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7978d 14h /pci/tags/rel_12/sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7978d 15h /pci/tags/rel_12/sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8017d 22h /pci/tags/rel_12/sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8020d 14h /pci/tags/rel_12/sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8026d 20h /pci/tags/rel_12/sim
42 Removed out of date files mihad 8038d 21h /pci/tags/rel_12/sim
30 Example of PCI testbench log file mihad 8198d 19h /pci/tags/rel_12/sim
27 Modified testbench and fixed some bugs mihad 8201d 14h /pci/tags/rel_12/sim
26 Modified testbench and fixed some bugs mihad 8201d 15h /pci/tags/rel_12/sim
22 Added short description for simulation running mihad 8219d 15h /pci/tags/rel_12/sim
20 *** empty log message *** mihad 8219d 16h /pci/tags/rel_12/sim
17 *** empty log message *** mihad 8219d 17h /pci/tags/rel_12/sim
16 Import of various scripts for simulation running mihad 8219d 17h /pci/tags/rel_12/sim

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