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[/] [pci/] [tags/] [rel_3/] [rtl/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5618d 12h /pci/tags/rel_3/rtl
74 This commit was manufactured by cvs2svn to create tag 'rel_3'. 7858d 05h /pci/tags/rel_3/rtl
73 Bug fixes, testcases added. mihad 7858d 05h /pci/tags/rel_3/rtl
72 *** empty log message *** mihad 7905d 08h /pci/tags/rel_3/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7913d 00h /pci/tags/rel_3/rtl
69 Changed BIST signal names etc.. mihad 7950d 08h /pci/tags/rel_3/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7953d 17h /pci/tags/rel_3/rtl
67 Changed BIST signals for RAMs. tadejm 7953d 22h /pci/tags/rel_3/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7957d 08h /pci/tags/rel_3/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7960d 06h /pci/tags/rel_3/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7960d 11h /pci/tags/rel_3/rtl
62 Added BIST signals for RAMs. mihad 7963d 03h /pci/tags/rel_3/rtl
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7971d 03h /pci/tags/rel_3/rtl
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7971d 05h /pci/tags/rel_3/rtl
58 Removed all logic from asynchronous reset network mihad 7976d 05h /pci/tags/rel_3/rtl
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7976d 11h /pci/tags/rel_3/rtl
56 Number of state bits define was removed mihad 7977d 02h /pci/tags/rel_3/rtl
55 Changed state machine encoding to true one-hot mihad 7977d 02h /pci/tags/rel_3/rtl
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8010d 07h /pci/tags/rel_3/rtl
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8010d 12h /pci/tags/rel_3/rtl

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