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[/] [pci/] [tags/] [rel_3/] [rtl/] [verilog/] - Rev 66

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Rev Log message Author Age Path
66 Changed empty status generation in pciw_fifo_control.v mihad 8040d 21h /pci/tags/rel_3/rtl/verilog
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 8043d 19h /pci/tags/rel_3/rtl/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 8043d 23h /pci/tags/rel_3/rtl/verilog
62 Added BIST signals for RAMs. mihad 8046d 16h /pci/tags/rel_3/rtl/verilog
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 8054d 16h /pci/tags/rel_3/rtl/verilog
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 8054d 17h /pci/tags/rel_3/rtl/verilog
58 Removed all logic from asynchronous reset network mihad 8059d 18h /pci/tags/rel_3/rtl/verilog
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 8060d 00h /pci/tags/rel_3/rtl/verilog
56 Number of state bits define was removed mihad 8060d 14h /pci/tags/rel_3/rtl/verilog
55 Changed state machine encoding to true one-hot mihad 8060d 15h /pci/tags/rel_3/rtl/verilog
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8093d 20h /pci/tags/rel_3/rtl/verilog
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8094d 00h /pci/tags/rel_3/rtl/verilog
50 Got rid of undef directives mihad 8096d 17h /pci/tags/rel_3/rtl/verilog
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8096d 17h /pci/tags/rel_3/rtl/verilog
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 8096d 17h /pci/tags/rel_3/rtl/verilog
47 Known issues repaired mihad 8096d 22h /pci/tags/rel_3/rtl/verilog
46 Include statement was enclosed in synosys translate off/on directive - repaired mihad 8101d 17h /pci/tags/rel_3/rtl/verilog
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8102d 22h /pci/tags/rel_3/rtl/verilog
35 Files updated with missing includes, resolved some race conditions in test bench mihad 8248d 02h /pci/tags/rel_3/rtl/verilog
33 Added some testcases, removed un-needed fifo signals mihad 8263d 22h /pci/tags/rel_3/rtl/verilog

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