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[/] [pci/] [tags/] [rel_4/] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5553d 01h	/pci/tags/rel_4
80	This commit was manufactured by cvs2svn to create tag 'rel_4'.		7786d 17h	/tags/rel_4
79	Updated.	mihad	7786d 17h	/trunk
78	Old files with wrong names removed.	mihad	7786d 17h	/trunk
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7786d 17h	/trunk
76	TRDY output delay was 10 instead of 11. Repaired.	mihad	7789d 16h	/trunk
75	Include statement moved out of off/on pragma as reported by Uwe.	mihad	7792d 17h	/trunk
73	Bug fixes, testcases added.	mihad	7792d 18h	/trunk
72	* empty log message *	mihad	7839d 21h	/trunk
71	Changed the code a bit to make it more readable. Functionality not changed in any way. More robust synchronization in fifos is still pending.	mihad	7847d 13h	/trunk
69	Changed BIST signal names etc..	mihad	7884d 21h	/trunk
68	Changed wrong signal name scanb_sen into scanb_en.	tadejm	7888d 06h	/trunk
67	Changed BIST signals for RAMs.	tadejm	7888d 11h	/trunk
66	Changed empty status generation in pciw_fifo_control.v	mihad	7891d 21h	/trunk
65	Cleaned up non-blocking assignments in combinatinal logic statements	mihad	7894d 19h	/trunk
64	The testcase I just added in previous revision repaired	mihad	7894d 22h	/trunk
63	Added additional testcase and changed rst name in BIST to trst	mihad	7895d 00h	/trunk
62	Added BIST signals for RAMs.	mihad	7897d 16h	/trunk
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7905d 16h	/trunk
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7905d 18h	/trunk

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[/] [pci/] [tags/] [rel_4/] - Rev 154

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