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[/] [pci/] [tags/] [rel_5/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5556d 22h /pci/tags/rel_5
82 This commit was manufactured by cvs2svn to create tag 'rel_5'. 7787d 08h /tags/rel_5
81 Updated synchronization in top level fifo modules. mihad 7787d 08h /trunk
79 Updated. mihad 7790d 13h /trunk
78 Old files with wrong names removed. mihad 7790d 14h /trunk
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7790d 14h /trunk
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7793d 13h /trunk
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7796d 14h /trunk
73 Bug fixes, testcases added. mihad 7796d 14h /trunk
72 *** empty log message *** mihad 7843d 18h /trunk
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.
mihad 7851d 10h /trunk
69 Changed BIST signal names etc.. mihad 7888d 17h /trunk
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7892d 03h /trunk
67 Changed BIST signals for RAMs. tadejm 7892d 08h /trunk
66 Changed empty status generation in pciw_fifo_control.v mihad 7895d 18h /trunk
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7898d 16h /trunk
64 The testcase I just added in previous revision repaired mihad 7898d 18h /trunk
63 Added additional testcase and changed rst name in BIST to trst mihad 7898d 20h /trunk
62 Added BIST signals for RAMs. mihad 7901d 13h /trunk
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7909d 13h /trunk

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