OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_6/] - Rev 69

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7922d 11h /pci/tags/rel_6
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7925d 21h /pci/tags/rel_6
67 Changed BIST signals for RAMs. tadejm 7926d 02h /pci/tags/rel_6
66 Changed empty status generation in pciw_fifo_control.v mihad 7929d 12h /pci/tags/rel_6
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7932d 10h /pci/tags/rel_6
64 The testcase I just added in previous revision repaired mihad 7932d 12h /pci/tags/rel_6
63 Added additional testcase and changed rst name in BIST to trst mihad 7932d 14h /pci/tags/rel_6
62 Added BIST signals for RAMs. mihad 7935d 07h /pci/tags/rel_6
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7943d 07h /pci/tags/rel_6
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7943d 08h /pci/tags/rel_6
58 Removed all logic from asynchronous reset network mihad 7948d 09h /pci/tags/rel_6
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7948d 14h /pci/tags/rel_6
56 Number of state bits define was removed mihad 7949d 05h /pci/tags/rel_6
55 Changed state machine encoding to true one-hot mihad 7949d 06h /pci/tags/rel_6
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7982d 07h /pci/tags/rel_6
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7982d 11h /pci/tags/rel_6
52 Oops, never before noticed that OC header is missing mihad 7982d 15h /pci/tags/rel_6
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7982d 15h /pci/tags/rel_6
50 Got rid of undef directives mihad 7985d 07h /pci/tags/rel_6
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7985d 08h /pci/tags/rel_6

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.