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[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] - Rev 154

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Rev	Log message	Author	Age	Path
154	New directory structure.	root	5584d 11h	/pci/tags/rel_6/sim/rtl_sim
112	This commit was manufactured by cvs2svn to create tag 'rel_6'.		7619d 06h	/pci/tags/rel_6/sim/rtl_sim
109	There was missing path to hdl.var file.	tadejm	7625d 02h	/pci/tags/rel_6/sim/rtl_sim
106	Added limited WISHBONE B3 support for WISHBONE Slave Unit. Doesn't support full speed bursts yet.	mihad	7630d 01h	/pci/tags/rel_6/sim/rtl_sim
104	Found and simulated the problem in the synchronization logic. Repaired the synchronization logic in the FIFOs.	mihad	7635d 11h	/pci/tags/rel_6/sim/rtl_sim
95	Removed this file, because it was too large - long download time.	mihad	7682d 09h	/pci/tags/rel_6/sim/rtl_sim
92	Update!	mihad	7682d 16h	/pci/tags/rel_6/sim/rtl_sim
81	Updated synchronization in top level fifo modules.	mihad	7814d 21h	/pci/tags/rel_6/sim/rtl_sim
77	Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.	mihad	7818d 02h	/pci/tags/rel_6/sim/rtl_sim
73	Bug fixes, testcases added.	mihad	7824d 03h	/pci/tags/rel_6/sim/rtl_sim
72	* empty log message *	mihad	7871d 07h	/pci/tags/rel_6/sim/rtl_sim
63	Added additional testcase and changed rst name in BIST to trst	mihad	7926d 09h	/pci/tags/rel_6/sim/rtl_sim
62	Added BIST signals for RAMs.	mihad	7929d 02h	/pci/tags/rel_6/sim/rtl_sim
60	Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!	mihad	7937d 02h	/pci/tags/rel_6/sim/rtl_sim
59	Added meta flop module for easier meta stable FF identification during synthesis	mihad	7937d 03h	/pci/tags/rel_6/sim/rtl_sim
51	Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions.	mihad	7976d 10h	/pci/tags/rel_6/sim/rtl_sim
49	Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives	mihad	7979d 02h	/pci/tags/rel_6/sim/rtl_sim
45	Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image	mihad	7985d 08h	/pci/tags/rel_6/sim/rtl_sim
42	Removed out of date files	mihad	7997d 09h	/pci/tags/rel_6/sim/rtl_sim
30	Example of PCI testbench log file	mihad	8157d 07h	/pci/tags/rel_6/sim/rtl_sim

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[/] [pci/] [tags/] [rel_6/] [sim/] [rtl_sim/] - Rev 154

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