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[/] [pci/] [tags/] [rel_7/] - Rev 69

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Rev Log message Author Age Path
69 Changed BIST signal names etc.. mihad 7969d 04h /pci/tags/rel_7
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7972d 14h /pci/tags/rel_7
67 Changed BIST signals for RAMs. tadejm 7972d 18h /pci/tags/rel_7
66 Changed empty status generation in pciw_fifo_control.v mihad 7976d 05h /pci/tags/rel_7
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7979d 03h /pci/tags/rel_7
64 The testcase I just added in previous revision repaired mihad 7979d 05h /pci/tags/rel_7
63 Added additional testcase and changed rst name in BIST to trst mihad 7979d 07h /pci/tags/rel_7
62 Added BIST signals for RAMs. mihad 7982d 00h /pci/tags/rel_7
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7990d 00h /pci/tags/rel_7
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7990d 01h /pci/tags/rel_7
58 Removed all logic from asynchronous reset network mihad 7995d 01h /pci/tags/rel_7
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7995d 07h /pci/tags/rel_7
56 Number of state bits define was removed mihad 7995d 22h /pci/tags/rel_7
55 Changed state machine encoding to true one-hot mihad 7995d 23h /pci/tags/rel_7
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 8029d 00h /pci/tags/rel_7
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 8029d 04h /pci/tags/rel_7
52 Oops, never before noticed that OC header is missing mihad 8029d 08h /pci/tags/rel_7
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8029d 08h /pci/tags/rel_7
50 Got rid of undef directives mihad 8032d 00h /pci/tags/rel_7
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8032d 00h /pci/tags/rel_7

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