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[/] [pci/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 106

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Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7678d 13h /pci/tags/rel_7/rtl/verilog
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7683d 22h /pci/tags/rel_7/rtl/verilog
94 Changed one critical PCI bus signal logic. mihad 7730d 20h /pci/tags/rel_7/rtl/verilog
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7808d 17h /pci/tags/rel_7/rtl/verilog
86 Entered the option to disable no response counter in wb master. mihad 7820d 15h /pci/tags/rel_7/rtl/verilog
83 Cleaned up the code. No functional changes. mihad 7849d 12h /pci/tags/rel_7/rtl/verilog
81 Updated synchronization in top level fifo modules. mihad 7863d 09h /pci/tags/rel_7/rtl/verilog
79 Updated. mihad 7866d 14h /pci/tags/rel_7/rtl/verilog
78 Old files with wrong names removed. mihad 7866d 14h /pci/tags/rel_7/rtl/verilog
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7866d 14h /pci/tags/rel_7/rtl/verilog
73 Bug fixes, testcases added. mihad 7872d 15h /pci/tags/rel_7/rtl/verilog
72 *** empty log message *** mihad 7919d 18h /pci/tags/rel_7/rtl/verilog
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7927d 10h /pci/tags/rel_7/rtl/verilog
69 Changed BIST signal names etc.. mihad 7964d 18h /pci/tags/rel_7/rtl/verilog
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7968d 03h /pci/tags/rel_7/rtl/verilog
67 Changed BIST signals for RAMs. tadejm 7968d 08h /pci/tags/rel_7/rtl/verilog
66 Changed empty status generation in pciw_fifo_control.v mihad 7971d 18h /pci/tags/rel_7/rtl/verilog
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7974d 16h /pci/tags/rel_7/rtl/verilog
63 Added additional testcase and changed rst name in BIST to trst mihad 7974d 20h /pci/tags/rel_7/rtl/verilog
62 Added BIST signals for RAMs. mihad 7977d 13h /pci/tags/rel_7/rtl/verilog

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