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[/] [pci/] [tags/] [rel_8/] - Rev 104

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Rev Log message Author Age Path
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7649d 01h /pci/tags/rel_8
103 Added test application and modified files to support it. mihad 7695d 22h /pci/tags/rel_8
102 Cleanup! mihad 7695d 22h /pci/tags/rel_8
101 Added simulation files. mihad 7695d 22h /pci/tags/rel_8
100 Cleanup! mihad 7695d 22h /pci/tags/rel_8
99 Cleanup! mihad 7695d 22h /pci/tags/rel_8
98 Cleanup. mihad 7695d 22h /pci/tags/rel_8
97 Doing a little bit of cleanup. mihad 7695d 22h /pci/tags/rel_8
96 Update! mihad 7695d 23h /pci/tags/rel_8
95 Removed this file, because it was too large - long download time. mihad 7695d 23h /pci/tags/rel_8
94 Changed one critical PCI bus signal logic. mihad 7695d 23h /pci/tags/rel_8
93 Added a test application! mihad 7696d 06h /pci/tags/rel_8
92 Update! mihad 7696d 06h /pci/tags/rel_8
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7731d 20h /pci/tags/rel_8
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7731d 20h /pci/tags/rel_8
89 Burst 2 error fixed. mihad 7767d 21h /pci/tags/rel_8
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7773d 20h /pci/tags/rel_8
87 Updated acording to RTL changes. mihad 7785d 17h /pci/tags/rel_8
86 Entered the option to disable no response counter in wb master. mihad 7785d 17h /pci/tags/rel_8
85 Changed Vendor ID defines. mihad 7785d 22h /pci/tags/rel_8

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