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[/] [pci/] [tags/] [rel_8/] - Rev 67

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Rev Log message Author Age Path
67 Changed BIST signals for RAMs. tadejm 7939d 14h /pci/tags/rel_8
66 Changed empty status generation in pciw_fifo_control.v mihad 7943d 00h /pci/tags/rel_8
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7945d 22h /pci/tags/rel_8
64 The testcase I just added in previous revision repaired mihad 7946d 01h /pci/tags/rel_8
63 Added additional testcase and changed rst name in BIST to trst mihad 7946d 02h /pci/tags/rel_8
62 Added BIST signals for RAMs. mihad 7948d 19h /pci/tags/rel_8
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7956d 19h /pci/tags/rel_8
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7956d 21h /pci/tags/rel_8
58 Removed all logic from asynchronous reset network mihad 7961d 21h /pci/tags/rel_8
57 Added completion expiration test for WB Slave unit. Changed expiration signalling mihad 7962d 03h /pci/tags/rel_8
56 Number of state bits define was removed mihad 7962d 17h /pci/tags/rel_8
55 Changed state machine encoding to true one-hot mihad 7962d 18h /pci/tags/rel_8
54 Changed Tsetup and Thold for WISHBONE models, due to difficulties encountered during gate level sim mihad 7995d 20h /pci/tags/rel_8
53 Updated for synthesis purposes. Gate level simulation was failing in some configurations mihad 7995d 23h /pci/tags/rel_8
52 Oops, never before noticed that OC header is missing mihad 7996d 03h /pci/tags/rel_8
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 7996d 03h /pci/tags/rel_8
50 Got rid of undef directives mihad 7998d 20h /pci/tags/rel_8
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 7998d 20h /pci/tags/rel_8
48 Extracted distributed RAM module from wb/pci_tpram.v to its own file mihad 7998d 20h /pci/tags/rel_8
47 Known issues repaired mihad 7999d 02h /pci/tags/rel_8

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