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[/] [pci/] [tags/] [rel_8/] [sim/] - Rev 95

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Rev Log message Author Age Path
95 Removed this file, because it was too large - long download time. mihad 7735d 02h /pci/tags/rel_8/sim
92 Update! mihad 7735d 10h /pci/tags/rel_8/sim
81 Updated synchronization in top level fifo modules. mihad 7867d 14h /pci/tags/rel_8/sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7870d 19h /pci/tags/rel_8/sim
73 Bug fixes, testcases added. mihad 7876d 20h /pci/tags/rel_8/sim
72 *** empty log message *** mihad 7924d 00h /pci/tags/rel_8/sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7979d 02h /pci/tags/rel_8/sim
62 Added BIST signals for RAMs. mihad 7981d 19h /pci/tags/rel_8/sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7989d 19h /pci/tags/rel_8/sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7989d 20h /pci/tags/rel_8/sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8029d 03h /pci/tags/rel_8/sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8031d 19h /pci/tags/rel_8/sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8038d 01h /pci/tags/rel_8/sim
42 Removed out of date files mihad 8050d 02h /pci/tags/rel_8/sim
30 Example of PCI testbench log file mihad 8210d 00h /pci/tags/rel_8/sim
27 Modified testbench and fixed some bugs mihad 8212d 19h /pci/tags/rel_8/sim
26 Modified testbench and fixed some bugs mihad 8212d 20h /pci/tags/rel_8/sim
22 Added short description for simulation running mihad 8230d 20h /pci/tags/rel_8/sim
20 *** empty log message *** mihad 8230d 21h /pci/tags/rel_8/sim
17 *** empty log message *** mihad 8230d 22h /pci/tags/rel_8/sim

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