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[/] [pci/] [tags/] [rel_WB_B3/] [apps/] - Rev 101

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Rev Log message Author Age Path
101 Added simulation files. mihad 7688d 08h /pci/tags/rel_WB_B3/apps
100 Cleanup! mihad 7688d 08h /pci/tags/rel_WB_B3/apps
99 Cleanup! mihad 7688d 09h /pci/tags/rel_WB_B3/apps
98 Cleanup. mihad 7688d 09h /pci/tags/rel_WB_B3/apps
97 Doing a little bit of cleanup. mihad 7688d 09h /pci/tags/rel_WB_B3/apps
96 Update! mihad 7688d 09h /pci/tags/rel_WB_B3/apps
93 Added a test application! mihad 7688d 16h /pci/tags/rel_WB_B3/apps
91 WebPack 5.2 constraint file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 06h /pci/tags/rel_WB_B3/apps
90 WebPack 5.2 project file for PCI CRT application was contributed by Uwe Bonnes (bon@elektron.ikp.physik.tu-darmstadt.de) tadejm 7724d 06h /pci/tags/rel_WB_B3/apps
85 Changed Vendor ID defines. mihad 7778d 08h /pci/tags/rel_WB_B3/apps
84 Changed vendor ID. mihad 7782d 02h /pci/tags/rel_WB_B3/apps
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7824d 02h /pci/tags/rel_WB_B3/apps
76 TRDY output delay was 10 instead of 11. Repaired. mihad 7827d 02h /pci/tags/rel_WB_B3/apps
75 Include statement moved out of off/on pragma as reported by Uwe. mihad 7830d 03h /pci/tags/rel_WB_B3/apps
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7943d 03h /pci/tags/rel_WB_B3/apps
38 This file is not needed tadej 8082d 03h /pci/tags/rel_WB_B3/apps
36 *** empty log message *** tadej 8082d 04h /pci/tags/rel_WB_B3/apps
31 User defined constants used for Test Application tadej 8162d 23h /pci/tags/rel_WB_B3/apps
29 Xilinx synthesys log file tadej 8163d 10h /pci/tags/rel_WB_B3/apps
25 *** empty log message *** mihad 8184d 01h /pci/tags/rel_WB_B3/apps

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