OpenCores
URL https://opencores.org/ocsvn/pci/pci/trunk

Subversion Repositories pci

[/] [pci/] [tags/] [rel_WB_B3/] [rtl/] - Rev 106

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7635d 11h /pci/tags/rel_WB_B3/rtl
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7640d 21h /pci/tags/rel_WB_B3/rtl
94 Changed one critical PCI bus signal logic. mihad 7687d 19h /pci/tags/rel_WB_B3/rtl
88 Added the reset value parameter to the synchronizer flop module.
Added resets to all synchronizer flop instances.
Repaired initial sync value in fifos.		 mihad 7765d 16h /pci/tags/rel_WB_B3/rtl
86 Entered the option to disable no response counter in wb master. mihad 7777d 14h /pci/tags/rel_WB_B3/rtl
83 Cleaned up the code. No functional changes. mihad 7806d 11h /pci/tags/rel_WB_B3/rtl
81 Updated synchronization in top level fifo modules. mihad 7820d 07h /pci/tags/rel_WB_B3/rtl
79 Updated. mihad 7823d 12h /pci/tags/rel_WB_B3/rtl
78 Old files with wrong names removed. mihad 7823d 12h /pci/tags/rel_WB_B3/rtl
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7823d 12h /pci/tags/rel_WB_B3/rtl
73 Bug fixes, testcases added. mihad 7829d 13h /pci/tags/rel_WB_B3/rtl
72 *** empty log message *** mihad 7876d 17h /pci/tags/rel_WB_B3/rtl
71 Changed the code a bit to make it more readable.
Functionality not changed in any way.
More robust synchronization in fifos is still pending.		 mihad 7884d 09h /pci/tags/rel_WB_B3/rtl
69 Changed BIST signal names etc.. mihad 7921d 16h /pci/tags/rel_WB_B3/rtl
68 Changed wrong signal name scanb_sen into scanb_en. tadejm 7925d 02h /pci/tags/rel_WB_B3/rtl
67 Changed BIST signals for RAMs. tadejm 7925d 06h /pci/tags/rel_WB_B3/rtl
66 Changed empty status generation in pciw_fifo_control.v mihad 7928d 17h /pci/tags/rel_WB_B3/rtl
65 Cleaned up non-blocking assignments in combinatinal logic statements mihad 7931d 15h /pci/tags/rel_WB_B3/rtl
63 Added additional testcase and changed rst name in BIST to trst mihad 7931d 19h /pci/tags/rel_WB_B3/rtl
62 Added BIST signals for RAMs. mihad 7934d 12h /pci/tags/rel_WB_B3/rtl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.