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[/] [pci/] [tags/] [rel_WB_B3/] [sim/] [rtl_sim/] - Rev 154

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Rev Log message Author Age Path
154 New directory structure. root 5621d 03h /pci/tags/rel_WB_B3/sim/rtl_sim
121 This commit was manufactured by cvs2svn to create tag 'rel_WB_B3'. 7648d 14h /pci/tags/rel_WB_B3/sim/rtl_sim
118 Some minor changes due to changes in core. tadejm 7648d 14h /pci/tags/rel_WB_B3/sim/rtl_sim
109 There was missing path to hdl.var file. tadejm 7661d 19h /pci/tags/rel_WB_B3/sim/rtl_sim
106 Added limited WISHBONE B3 support for WISHBONE Slave Unit.
Doesn't support full speed bursts yet.		 mihad 7666d 17h /pci/tags/rel_WB_B3/sim/rtl_sim
104 Found and simulated the problem in the synchronization logic.
Repaired the synchronization logic in the FIFOs.		 mihad 7672d 03h /pci/tags/rel_WB_B3/sim/rtl_sim
95 Removed this file, because it was too large - long download time. mihad 7719d 01h /pci/tags/rel_WB_B3/sim/rtl_sim
92 Update! mihad 7719d 09h /pci/tags/rel_WB_B3/sim/rtl_sim
81 Updated synchronization in top level fifo modules. mihad 7851d 13h /pci/tags/rel_WB_B3/sim/rtl_sim
77 Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed. mihad 7854d 19h /pci/tags/rel_WB_B3/sim/rtl_sim
73 Bug fixes, testcases added. mihad 7860d 19h /pci/tags/rel_WB_B3/sim/rtl_sim
72 *** empty log message *** mihad 7907d 23h /pci/tags/rel_WB_B3/sim/rtl_sim
63 Added additional testcase and changed rst name in BIST to trst mihad 7963d 01h /pci/tags/rel_WB_B3/sim/rtl_sim
62 Added BIST signals for RAMs. mihad 7965d 18h /pci/tags/rel_WB_B3/sim/rtl_sim
60 Added support for Virtual Silicon two port RAM. Didn't run regression on it yet! mihad 7973d 18h /pci/tags/rel_WB_B3/sim/rtl_sim
59 Added meta flop module for easier meta stable FF identification during synthesis mihad 7973d 19h /pci/tags/rel_WB_B3/sim/rtl_sim
51 Fixed a bug and provided testcase for it. Target was responding to configuration cycle type 1 transactions. mihad 8013d 02h /pci/tags/rel_WB_B3/sim/rtl_sim
49 Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives mihad 8015d 18h /pci/tags/rel_WB_B3/sim/rtl_sim
45 Added a few testcases. Repaired wrong reset value for PCI_AM5 register. Repaired Parity Error Detected bit setting. Changed PCI_AM0 to always enabled(regardles of PCI_AM0 define), if image 0 is used as configuration image mihad 8022d 00h /pci/tags/rel_WB_B3/sim/rtl_sim
42 Removed out of date files mihad 8034d 01h /pci/tags/rel_WB_B3/sim/rtl_sim

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