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[/] [pit/] [trunk] - Rev 24

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Rev	Log message	Author	Age	Path
24	Added System Verilog Wishbone interface to module and testbench.	rehayes	4631d 19h	/pit/trunk
23	Simple language upgrade, will make bigger changes to add more system verilog features later.	rehayes	4717d 06h	/pit/trunk
22	Correct revision, compiles with VCS.	rehayes	4717d 06h	/pit/trunk
21	Simple language upgrade	rehayes	4717d 23h	/pit/trunk
20	minor update for timing constraint sugestions.	rehayes	5253d 00h	/pit/trunk
19	Minor change to add parameter to pit instance	rehayes	5253d 01h	/pit/trunk
18	Traded 16 data registers for 3 address registers when wait states are enabled.	rehayes	5253d 03h	/pit/trunk
17	Change WISHBONE ack signal so no output is generated when wait states are enabled and the bus transaction is terminated in the first cycle.	rehayes	5267d 00h	/pit/trunk
16	Added master error counter variable, added simulation timout limit	rehayes	5378d 03h	/pit/trunk
15	Fix blocking assigment	rehayes	5406d 03h	/pit/trunk
14	Cosmetic update, changed no-blocking assigment to blocking assigment	rehayes	5475d 01h	/pit/trunk
13	Update to rev 0.3, added SINGLE_CYCLE parameter	rehayes	5505d 05h	/pit/trunk
12	Fixed for single cycle reads	rehayes	5506d 00h	/pit/trunk
11	Changed read task to capture data at rising edge of clock	rehayes	5506d 00h	/pit/trunk
10	Added SINGLE_CYCLE parameter for WISHBONE bus cycles	rehayes	5507d 03h	/pit/trunk
9	fix problem with wb_wacc signal. Old method allowed data to be clocked into register twice.	rehayes	5512d 20h	/pit/trunk
8	Fix ack signal in testbench	rehayes	5512d 21h	/pit/trunk
7	Reflection of minor corrections	rehayes	5517d 03h	/pit/trunk
6	Reflection of minor corrections	rehayes	5517d 03h	/pit/trunk
5		rehayes	5554d 23h	/pit/trunk

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[/] [pit/] [trunk] - Rev 24

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