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[/] [plasma/] [tags/] [V3_0/] [vhdl/] - Rev 352

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Rev	Log message	Author	Age	Path
352		linus	5571d 05h	/plasma/tags/V3_0/vhdl
350		root	5600d 00h	/plasma/tags/V3_0/vhdl
140	This commit was manufactured by cvs2svn to create tag 'V3_0'.		6700d 13h	/plasma/tags/V3_0/vhdl
139	Major changes -- updated to Plasma Version 3	rhoads	6700d 13h	/plasma/tags/V3_0/vhdl
132	Changed "GENERIC" string to "DEFAULT" to be Xilinx friendly.	rhoads	7180d 11h	/plasma/tags/V3_0/vhdl
131	Changed "GENERIC" to "DEFAULT" to be Xilinx friendly.	rhoads	7180d 11h	/plasma/tags/V3_0/vhdl
129	Added reset_in to sensitivity list	rhoads	7199d 11h	/plasma/tags/V3_0/vhdl
128	Reset all registers, constants now upper case.	rhoads	7317d 22h	/plasma/tags/V3_0/vhdl
125	Fixed pc_source_type comment.	rhoads	7336d 12h	/plasma/tags/V3_0/vhdl
124	Holger Lohn's fix for interrupts when 3-state pipeline enabled.	rhoads	7336d 12h	/plasma/tags/V3_0/vhdl
123	Uncomment out the Altera portion. Xilinx users may need to re-comment out this section.	rhoads	7403d 12h	/plasma/tags/V3_0/vhdl
122	Added comment to explain why c_bus isn't delayed but reg_dest is delayed.	rhoads	7467d 13h	/plasma/tags/V3_0/vhdl
121	Added Matthias Gruenewald's tri-state area-optimized option	rhoads	7479d 01h	/plasma/tags/V3_0/vhdl
120	Make generics "GENERIC"	rhoads	7479d 01h	/plasma/tags/V3_0/vhdl
119	Opcodes from count.c	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl
118	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7517d 12h	/plasma/tags/V3_0/vhdl

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[/] [plasma/] [tags/] [V3_0/] [vhdl/] - Rev 352

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