OpenCores
URL https://opencores.org/ocsvn/rise/rise/trunk

Subversion Repositories rise

[/] [rise/] [trunk/] [vhdl/] - Rev 40

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
40 - Added seperate memory output vector to MEM_WB_REGISTER.
- Added status register to MEM_WB_REGISTER.
jlechner 6452d 21h /rise/trunk/vhdl
39 - Added wr_enable signals for imem and dmem
- Changed signals for register lock unit (this concerns id-stage and write-back-stage)
jlechner 6452d 21h /rise/trunk/vhdl
38 Memory output signal is now passed on asynchronously to write back stage. jlechner 6452d 21h /rise/trunk/vhdl
37 Applied VHDL indent. jlechner 6452d 21h /rise/trunk/vhdl
36 - Testbench for RISE. cwalter 6452d 21h /rise/trunk/vhdl
35 - Testbench for register file. cwalter 6452d 21h /rise/trunk/vhdl
34 - Filex have been renamed to have tb prefix. cwalter 6452d 21h /rise/trunk/vhdl
33 - Fixed process sensitivity list. cwalter 6452d 22h /rise/trunk/vhdl
32 - When this stage asserts stall_out it must clear the input for the next
stage.
- Fixed process sensitivity list.
cwalter 6452d 22h /rise/trunk/vhdl
31 - Added PC_RESET_VECTOR constant. cwalter 6452d 23h /rise/trunk/vhdl
30 - Top level testbench for RISE. cwalter 6452d 23h /rise/trunk/vhdl
29 - Initial version of IF stage with dummy instructions. cwalter 6452d 23h /rise/trunk/vhdl
28 Added new register write enable signals. jlechner 6454d 17h /rise/trunk/vhdl
27 Added new register write enable signals to component instantiation of register_file and wb_stage. jlechner 6454d 17h /rise/trunk/vhdl
26 Applied VHDL indent. jlechner 6454d 17h /rise/trunk/vhdl
25 netlist file for the memories
is needed for IMEM and DMEM
ustadler 6455d 17h /rise/trunk/vhdl
24 4k Data Instruction for Spartan 3 (Block RAM)
Added write enable to the entity
ustadler 6455d 17h /rise/trunk/vhdl
23 4k Data Memory for Spartan 3 (Block RAM)
Added write enable to the entity
ustadler 6455d 17h /rise/trunk/vhdl
22 testbench für die register file ustadler 6456d 06h /rise/trunk/vhdl
21 überarbeitet. asynchrones lesen und synchrones schreiben. dreg_enable, sr_enable und lr_enable zur entity hinzugefügt ustadler 6456d 18h /rise/trunk/vhdl

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.