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[/] [sdr_ctrl/] [trunk/] - Rev 59

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Rev Log message Author Age Path
59 Control path request and data are register now for better FPGA timing dinesha 4498d 09h /sdr_ctrl/trunk
58 Read Data is register on RD_FAST=0 case dinesha 4498d 09h /sdr_ctrl/trunk
57 Synthesis constraints are added dinesha 4498d 23h /sdr_ctrl/trunk
56 FPGA Synth optimisation dinesha 4499d 00h /sdr_ctrl/trunk
55 FPGA Synthesis timing optimisation dinesha 4499d 01h /sdr_ctrl/trunk
54 FPGA Timing Optimisation dinesha 4501d 22h /sdr_ctrl/trunk
53 Test bench upgradation dinesha 4502d 23h /sdr_ctrl/trunk
52 Documentation update for request control and transfer control block dinesha 4502d 23h /sdr_ctrl/trunk
51 FPGA relating timing optimisation done dinesha 4502d 23h /sdr_ctrl/trunk
50 Bug fix the request length is fixe dinesha 4505d 03h /sdr_ctrl/trunk
49 clean up dinesha 4506d 02h /sdr_ctrl/trunk
48 top-level cleanup dinesha 4506d 02h /sdr_ctrl/trunk
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4506d 02h /sdr_ctrl/trunk
46 test bench upgrade + rtl cleanup dinesha 4508d 03h /sdr_ctrl/trunk
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4508d 07h /sdr_ctrl/trunk
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4510d 05h /sdr_ctrl/trunk
43 Test bench automation to handle differ write/read burst sequence is supported now dinesha 4510d 07h /sdr_ctrl/trunk
42 Bug fix in read access is fixed dinesha 4510d 07h /sdr_ctrl/trunk
41 Updated Spec ver 0.1 is added back to svn dinesha 4510d 09h /sdr_ctrl/trunk
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4511d 02h /sdr_ctrl/trunk

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