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[/] [sdr_ctrl/] [trunk/] [rtl/] - Rev 59

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Rev Log message Author Age Path
59 Control path request and data are register now for better FPGA timing dinesha 4491d 16h /sdr_ctrl/trunk/rtl
58 Read Data is register on RD_FAST=0 case dinesha 4491d 17h /sdr_ctrl/trunk/rtl
55 FPGA Synthesis timing optimisation dinesha 4492d 08h /sdr_ctrl/trunk/rtl
54 FPGA Timing Optimisation dinesha 4495d 06h /sdr_ctrl/trunk/rtl
51 FPGA relating timing optimisation done dinesha 4496d 07h /sdr_ctrl/trunk/rtl
50 Bug fix the request length is fixe dinesha 4498d 11h /sdr_ctrl/trunk/rtl
47 SDRAM bus converter bug fix and top-level signal clean up dinesha 4499d 10h /sdr_ctrl/trunk/rtl
46 test bench upgrade + rtl cleanup dinesha 4501d 10h /sdr_ctrl/trunk/rtl
45 RTL clean up and logic seperation done from sdram bus converter and request generator dinesha 4501d 15h /sdr_ctrl/trunk/rtl
44 SDRAM data path logic is modified to support 4 command line pipe line of different bank dinesha 4503d 13h /sdr_ctrl/trunk/rtl
42 Bug fix in read access is fixed dinesha 4503d 15h /sdr_ctrl/trunk/rtl
40 Application layer Fifo full conditional are register now to synth timing fixes dinesha 4504d 09h /sdr_ctrl/trunk/rtl
38 Port Name clean up dinesha 4505d 14h /sdr_ctrl/trunk/rtl
37 SDRAM dq and sdram pad clock are termindated inside the top rtl files dinesha 4505d 16h /sdr_ctrl/trunk/rtl
36 Clean up dinesha 4506d 07h /sdr_ctrl/trunk/rtl
33 clean up dinesha 4506d 09h /sdr_ctrl/trunk/rtl
31 Integrated SDRAM controller with wishbone interface is added into SVN dinesha 4508d 08h /sdr_ctrl/trunk/rtl
23 Pad sdram clock added and read path register w.r.t pad sdram clock dinesha 4510d 12h /sdr_ctrl/trunk/rtl
16 8 Bit SDRAM Support is added dinesha 4512d 07h /sdr_ctrl/trunk/rtl
15 Port cleanup dinesha 4515d 08h /sdr_ctrl/trunk/rtl

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