URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 125

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Rev	Log message	Author	Age	Path
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4171d 13h	/socgen/trunk/tools/bin
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4224d 16h	/socgen/trunk/tools/bin
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4285d 18h	/socgen/trunk/tools/bin
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4320d 12h	/socgen/trunk/tools/bin
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4355d 21h	/socgen/trunk/tools/bin
117	added yellow pages tools	jt_eaton	4383d 16h	/socgen/trunk/tools/bin
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4474d 17h	/socgen/trunk/tools/bin
113	started refactoring or1200	jt_eaton	4480d 10h	/socgen/trunk/tools/bin
112	added more test sims removed unneeded files	jt_eaton	4489d 23h	/socgen/trunk/tools/bin
106	checked in orp_soc project step 2	jt_eaton	4513d 16h	/socgen/trunk/tools/bin
100	created workspace prroject=fpga_mrisc for single compile general cleanup	jt_eaton	4613d 18h	/socgen/trunk/tools/bin
99	moved all projects into /projects/opencores.org added build_register added fizzim	jt_eaton	4656d 11h	/socgen/trunk/tools/bin
97	changed sim run directory to icarus added ise directory into syn added _tb testbench file to all sims	jt_eaton	4692d 16h	/socgen/trunk/tools/bin
94	socgen now supports both sim and syn views now allow each xml file to set its destination	jt_eaton	4802d 11h	/socgen/trunk/tools/bin
93	build scripts now support model views linting and coverage starting to work again	jt_eaton	4815d 00h	/socgen/trunk/tools/bin
90	now build all testbenches from ip-xact files and list as testbench in design.soc	jt_eaton	4828d 11h	/socgen/trunk/tools/bin
88	added xml files for test benches added gEDA sym sch starter templates	jt_eaton	4849d 20h	/socgen/trunk/tools/bin
86	split out all fpgas into families added fpga pad_ring level	jt_eaton	4868d 10h	/socgen/trunk/tools/bin
85	moved all synthesis into fpgas lib fixed memory leak in recursive routines	jt_eaton	4875d 09h	/socgen/trunk/tools/bin
84	removed unneeded files	jt_eaton	4925d 14h	/socgen/trunk/tools/bin

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[/] [socgen/] [trunk/] [tools/] [bin/] - Rev 125

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