URL https://opencores.org/ocsvn/socgen/socgen/trunk

Subversion Repositories socgen

[/] [socgen/] [trunk/] [tools] - Rev 135

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Rev	Log message	Author	Age	Path
135	resynced with socgen, Release V1.0.0 changed tool lic to apache 2.0	jt_eaton	2814d 03h	/socgen/trunk/tools
134	Resynced database socgen now supports elaboration Bad news is that it is now alot slower.	jt_eaton	3324d 04h	/socgen/trunk/tools
133	Added Desing databases and foundation for elaborations tools	jt_eaton	3367d 05h	/socgen/trunk/tools
131	Added elaboration databases and tools Added bus map creation tools	jt_eaton	3399d 02h	/socgen/trunk/tools
130	Dec 2014 major release trimmed out some IP replaced perl database with Berkeley	jt_eaton	3502d 19h	/socgen/trunk/tools
128	major cleanup added toolflows for sim,syn,documentation,linting and verilog added documentation tools	jt_eaton	3958d 01h	/socgen/trunk/tools
127	final cleanup before DAC	jt_eaton	4072d 22h	/socgen/trunk/tools
126	added mor1kx cleanup	jt_eaton	4126d 03h	/socgen/trunk/tools
125	Added two new 6502 cores in www.6502.org cleaned up sogen xml files and added module name control	jt_eaton	4170d 20h	/socgen/trunk/tools
124	beta release candidate 1 changed design.xml name aligned schema with filesystem	jt_eaton	4223d 23h	/socgen/trunk/tools
123	added support for ubuntu 12.10	jt_eaton	4238d 16h	/socgen/trunk/tools
122	Moved Nexys2 from opencores.org to digilentinc.com Moved jtag_rpc and or1k Busdefs into cde_jtag and or1200 components	jt_eaton	4246d 19h	/socgen/trunk/tools
121	cleaned up sims, added autogenerated test bench files removed mrisc and experimental or1k code	jt_eaton	4267d 01h	/socgen/trunk/tools
120	clean up componentGenerators names and directories sim + lint now synthesis TestBench	jt_eaton	4285d 01h	/socgen/trunk/tools
119	moved copyright files into /verilog changed cde copyright to apache from gplv3 split out tools into separate subdirectories changed design.xml files to socgen: namespace	jt_eaton	4319d 19h	/socgen/trunk/tools
118	optimized gen_verilog added padring support added configuration support added jtag sims added accellera candidate bus defs	jt_eaton	4355d 05h	/socgen/trunk/tools
117	added yellow pages tools	jt_eaton	4382d 23h	/socgen/trunk/tools
116	added build_header now use build_register for all spr components resynced or1200 code back to use orbuild toolchain	jt_eaton	4417d 21h	/socgen/trunk/tools
115	split or1200_cpu up into all ip-xact components removed dead files	jt_eaton	4462d 01h	/socgen/trunk/tools
114	moved or1200 connectivity out of verilog and into ip-xact added or1200_boot block removed force of 00 on lowest iwb_addr bits	jt_eaton	4474d 01h	/socgen/trunk/tools

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[/] [socgen/] [trunk/] [tools] - Rev 135

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