OpenCores
URL https://opencores.org/ocsvn/spdif_interface/spdif_interface/trunk

Subversion Repositories spdif_interface

[/] [spdif_interface/] [tags/] [rx_beta_1/] - Rev 73

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
73 New directory structure. root 5601d 19h /spdif_interface/tags/rx_beta_1
43 This commit was manufactured by cvs2svn to create tag 'rx_beta_1'. 7303d 12h /tags/rx_beta_1
42 Fixed bug with lock event generation. gedra 7303d 12h /trunk
41 Test bench update. gedra 7303d 12h /trunk
40 Improved test bench. gedra 7304d 12h /trunk
39 Bug-fix. gedra 7304d 12h /trunk
38 Signal renaming and bug fix. gedra 7318d 12h /trunk
37 Converted to numeric_std and fixed a few bugs. gedra 7319d 14h /trunk
36 Top level entity for receiver. gedra 7319d 14h /trunk
35 Top level test bench for receiver. NB! Not complete. gedra 7319d 14h /trunk
34 Converter to numeric_std and added hex functions gedra 7319d 15h /trunk
33 Minor update. gedra 7319d 15h /trunk
32 Wishbone bus utilities. gedra 7321d 09h /trunk
31 Added data output. gedra 7321d 09h /trunk
30 Added Wishbone bus cycle decoder. gedra 7322d 11h /trunk
29 Wishbone bus cycle decoder. gedra 7322d 11h /trunk
28 Delint'ed and changed name of architecture. gedra 7326d 19h /trunk
27 Alternate dual port memory implementation for Altera FPGA's. gedra 7327d 10h /trunk
26 Fixed a few bugs. gedra 7329d 10h /trunk
25 Changed status reg. declaration gedra 7329d 10h /trunk

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.