URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_1_beta/] - Rev 294

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5633d 17h	/t48/tags/rel_0_1_beta
251	This commit was manufactured by cvs2svn to create tag 'rel_0_1_beta'.		6604d 02h	/tags/rel_0_1_beta
88	allow memory bank switching during interrupts	arniml	7407d 10h	/trunk
87	abort gracfullt if memory bank switching does not work	arniml	7407d 10h	/trunk
86	update notice about expander port instructions	arniml	7407d 15h	/trunk
85	initial check-in	arniml	7407d 15h	/trunk
84	add if_timing module	arniml	7413d 06h	/trunk
83	connect if_timing to P2 output of T48	arniml	7413d 06h	/trunk
82	check expander timings	arniml	7413d 06h	/trunk
81	initial check-in	arniml	7413d 11h	/trunk
80	added if_timing	arniml	7413d 11h	/trunk
79	add if_timing module	arniml	7413d 11h	/trunk
78	adjust external timing of BUS	arniml	7413d 11h	/trunk
77	move from std_logic_arith to numeric_std	arniml	7414d 03h	/trunk
76	initial check-in	arniml	7414d 07h	/trunk
75	remove obsolete design unit	arniml	7414d 07h	/trunk
74	enhance pass/fail detection	arniml	7414d 16h	/trunk
73	removed dummy_s - workaround not longer needed for GHDL 0.11.1	arniml	7414d 16h	/trunk
72	removed superfluous signal from sensitivity list	arniml	7414d 16h	/trunk
71	add T8039 and its testbench	arniml	7420d 08h	/trunk