URL https://opencores.org/ocsvn/t48/t48/trunk

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[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] - Rev 292

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Rev	Log message	Author	Age	Path
292	New directory structure.	root	5638d 10h	/t48/tags/rel_0_2_beta/sw
252	This commit was manufactured by cvs2svn to create tag 'rel_0_2_beta'.		6608d 19h	/t48/tags/rel_0_2_beta/sw
113	generate two ROM files based on address: + 0 - 2047 : 2k internal ROM + 2048 - 4095 : 2k external ROM	arniml	7392d 09h	/t48/tags/rel_0_2_beta/sw
104	add white_box directory to test suite	arniml	7396d 06h	/t48/tags/rel_0_2_beta/sw
102	update for changes in address space of external memory	arniml	7396d 06h	/t48/tags/rel_0_2_beta/sw
99	initial check-in	arniml	7396d 06h	/t48/tags/rel_0_2_beta/sw
97	initial check-in	arniml	7396d 06h	/t48/tags/rel_0_2_beta/sw
96	select dedicated directorie(s) for regression	arniml	7397d 04h	/t48/tags/rel_0_2_beta/sw
95	check counter inactivity	arniml	7397d 04h	/t48/tags/rel_0_2_beta/sw
94	initial check-in	arniml	7397d 04h	/t48/tags/rel_0_2_beta/sw
90	intial check-in	arniml	7397d 05h	/t48/tags/rel_0_2_beta/sw
89	initial check-in	arniml	7411d 01h	/t48/tags/rel_0_2_beta/sw
88	allow memory bank switching during interrupts	arniml	7412d 03h	/t48/tags/rel_0_2_beta/sw
87	abort gracfullt if memory bank switching does not work	arniml	7412d 03h	/t48/tags/rel_0_2_beta/sw
85	initial check-in	arniml	7412d 08h	/t48/tags/rel_0_2_beta/sw
74	enhance pass/fail detection	arniml	7419d 09h	/t48/tags/rel_0_2_beta/sw
70	clean test cell before make	arniml	7425d 01h	/t48/tags/rel_0_2_beta/sw
69	fix name of istrobe	arniml	7425d 01h	/t48/tags/rel_0_2_beta/sw
61	expand script for dump compare	arniml	7426d 22h	/t48/tags/rel_0_2_beta/sw
58	add periodic interrupt	arniml	7427d 22h	/t48/tags/rel_0_2_beta/sw

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Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_2_beta/] [sw/] - Rev 292

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