URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 23

Rev	Log message	Author	Age	Path
23	rework Port 2 expander handling	arniml	7442d 13h	/t48/tags/rel_0_5_beta
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7442d 13h	/t48/tags/rel_0_5_beta
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7442d 13h	/t48/tags/rel_0_5_beta
20	move code for PROG out of if-branch for xtal3_s	arniml	7442d 13h	/t48/tags/rel_0_5_beta
19	enhance simulation result string	arniml	7444d 03h	/t48/tags/rel_0_5_beta
18	fix constant format	arniml	7444d 03h	/t48/tags/rel_0_5_beta
17	fix test	arniml	7444d 03h	/t48/tags/rel_0_5_beta
16	fix header	arniml	7444d 03h	/t48/tags/rel_0_5_beta
15	initial check-in	arniml	7445d 02h	/t48/tags/rel_0_5_beta
14	initial check-in	arniml	7445d 03h	/t48/tags/rel_0_5_beta
12	Imported sources	arniml	7445d 03h	/t48/tags/rel_0_5_beta
11	add description	arniml	7445d 04h	/t48/tags/rel_0_5_beta
10	put ext_ram on falling clock edge to sample the write enable proberly	arniml	7446d 03h	/t48/tags/rel_0_5_beta
9	initial check-in	arniml	7446d 03h	/t48/tags/rel_0_5_beta
8	initial check-in	arniml	7446d 04h	/t48/tags/rel_0_5_beta
7	initial check-in	arniml	7446d 04h	/t48/tags/rel_0_5_beta
6	moved to system directory	arniml	7446d 04h	/t48/tags/rel_0_5_beta
5	initial check-in	arniml	7447d 04h	/t48/tags/rel_0_5_beta
4	initial check-in	arniml	7447d 04h	/t48/tags/rel_0_5_beta
3	bummer	arniml	7447d 04h	/t48/tags/rel_0_5_beta