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[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 294

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Rev Log message Author Age Path
292 New directory structure. root 5587d 04h /t48/tags/rel_0_5_beta
255 This commit was manufactured by cvs2svn to create tag 'rel_0_5_beta'. 6557d 12h /tags/rel_0_5_beta
147 initial check-in for release 0.5 BETA arniml 7182d 16h /trunk
146 add bug
RD' and WR' not asserted for INS A, BUS and OUTL BUS, A
arniml 7183d 16h /trunk
145 remove PROG and end of XTAL2, see comment for details arniml 7183d 17h /trunk
144 delay db_dir_o by one machine cycle
this fixes the timing relation between BUS data and WR'
arniml 7183d 17h /trunk
143 Fix bug report:
"RD' and WR' not asserted for INS A, BUS and OUTL BUS, A"
rd is asserted for INS A, BUS
wr is asserted for OUTL BUS, A
P1, P2 and BUS are written in first instruction cycle
arniml 7183d 18h /trunk
142 deassert rd_q, wr_q and prog_q at end of XTAL3 arniml 7183d 18h /trunk
141 disable external memory to avoid conflicts with outl a, bus arniml 7183d 18h /trunk
140 remove tAW sanity check
conflicts with OUTL A, BUS
arniml 7183d 18h /trunk
139 add bug
P1 constantly in push-pull mode in t8048
arniml 7185d 04h /trunk
138 Fix for:
P1 constantly in push-pull mode in t8048
arniml 7185d 04h /trunk
137 add link to COMPILE_LIST arniml 7222d 17h /trunk
136 initial check-in arniml 7222d 17h /trunk
135 add bug
PSENn Timing
arniml 7227d 03h /trunk
134 Fix bug report:
"PSENn Timing"
PSEN is now only asserted for the second cycle if explicitely
requested by assert_psen_s.
The previous implementation asserted PSEN together with RD or WR.
arniml 7227d 13h /trunk
133 add checks for PSEN arniml 7227d 13h /trunk
132 stop simulation upon assertion error arniml 7227d 13h /trunk
131 update arniml 7227d 13h /trunk
130 initial check-in arniml 7227d 13h /trunk

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