URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_0_5_beta/] - Rev 35

Rev	Log message	Author	Age	Path
35	initial check-in	arniml	7437d 19h	/t48/tags/rel_0_5_beta
34	fix test wrt AC	arniml	7440d 19h	/t48/tags/rel_0_5_beta
33	rename pX_limp to pX_low_imp	arniml	7440d 20h	/t48/tags/rel_0_5_beta
32	rename pX_limp to pX_low_imp	arniml	7440d 20h	/t48/tags/rel_0_5_beta
31	refer PROJECT_DIR variable	arniml	7440d 20h	/t48/tags/rel_0_5_beta
30	connect prog_n_o	arniml	7441d 18h	/t48/tags/rel_0_5_beta
29	take auxiliary carry from direct ALU connection	arniml	7441d 18h	/t48/tags/rel_0_5_beta
28	update wiring for DA support	arniml	7441d 18h	/t48/tags/rel_0_5_beta
27	implemented mnemonic DA	arniml	7441d 18h	/t48/tags/rel_0_5_beta
26	support for DA instruction	arniml	7441d 18h	/t48/tags/rel_0_5_beta
25	initial check-in	arniml	7441d 18h	/t48/tags/rel_0_5_beta
24	connect control signal for Port 2 expander	arniml	7442d 02h	/t48/tags/rel_0_5_beta
23	rework Port 2 expander handling	arniml	7442d 02h	/t48/tags/rel_0_5_beta
22	merge MN_ANLD, MN_MOVD_PP_A and MN_ORLD_PP_A to OUTLD_PP_A	arniml	7442d 02h	/t48/tags/rel_0_5_beta
21	implement mnemonics: + MOVD_A_PP + OUTD_PP_A -> ANLD PP, A; MOVD PP, A; ORLD PP, A	arniml	7442d 02h	/t48/tags/rel_0_5_beta
20	move code for PROG out of if-branch for xtal3_s	arniml	7442d 03h	/t48/tags/rel_0_5_beta
19	enhance simulation result string	arniml	7443d 17h	/t48/tags/rel_0_5_beta
18	fix constant format	arniml	7443d 17h	/t48/tags/rel_0_5_beta
17	fix test	arniml	7443d 17h	/t48/tags/rel_0_5_beta
16	fix header	arniml	7443d 17h	/t48/tags/rel_0_5_beta