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[/] [t48/] [tags/] [rel_0_6_1_beta/] [sw/] - Rev 173

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Rev Log message Author Age Path
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6970d 22h /t48/tags/rel_0_6_1_beta/sw
141 disable external memory to avoid conflicts with outl a, bus arniml 7196d 21h /t48/tags/rel_0_6_1_beta/sw
132 stop simulation upon assertion error arniml 7240d 16h /t48/tags/rel_0_6_1_beta/sw
131 update arniml 7240d 16h /t48/tags/rel_0_6_1_beta/sw
130 initial check-in arniml 7240d 16h /t48/tags/rel_0_6_1_beta/sw
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge		 arniml 7310d 05h /t48/tags/rel_0_6_1_beta/sw
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell		 arniml 7310d 05h /t48/tags/rel_0_6_1_beta/sw
125 exclude from dump compare arniml 7310d 05h /t48/tags/rel_0_6_1_beta/sw
124 fix wrong handling of MB after return from interrupt arniml 7311d 02h /t48/tags/rel_0_6_1_beta/sw
123 support hex file for external ROM arniml 7311d 02h /t48/tags/rel_0_6_1_beta/sw
122 test MB after return from interrupt arniml 7311d 02h /t48/tags/rel_0_6_1_beta/sw
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7313d 20h /t48/tags/rel_0_6_1_beta/sw
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7354d 05h /t48/tags/rel_0_6_1_beta/sw
104 add white_box directory to test suite arniml 7358d 02h /t48/tags/rel_0_6_1_beta/sw
102 update for changes in address space of external memory arniml 7358d 02h /t48/tags/rel_0_6_1_beta/sw
99 initial check-in arniml 7358d 02h /t48/tags/rel_0_6_1_beta/sw
97 initial check-in arniml 7358d 03h /t48/tags/rel_0_6_1_beta/sw
96 select dedicated directorie(s) for regression arniml 7359d 00h /t48/tags/rel_0_6_1_beta/sw
95 check counter inactivity arniml 7359d 00h /t48/tags/rel_0_6_1_beta/sw
94 initial check-in arniml 7359d 00h /t48/tags/rel_0_6_1_beta/sw

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