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[/] [t48/] [tags/] [rel_0_6_beta/] [sw/] - Rev 294

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292 New directory structure. root 5589d 05h /t48/tags/rel_0_6_beta/sw
258 This commit was manufactured by cvs2svn to create tag 'rel_0_6_beta'. 6559d 14h /t48/tags/rel_0_6_beta/sw
185 initial check-in arniml 6868d 18h /t48/tags/rel_0_6_beta/sw
184 initial check-in arniml 6868d 19h /t48/tags/rel_0_6_beta/sw
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"
arniml 6959d 20h /t48/tags/rel_0_6_beta/sw
141 disable external memory to avoid conflicts with outl a, bus arniml 7185d 20h /t48/tags/rel_0_6_beta/sw
132 stop simulation upon assertion error arniml 7229d 15h /t48/tags/rel_0_6_beta/sw
131 update arniml 7229d 15h /t48/tags/rel_0_6_beta/sw
130 initial check-in arniml 7229d 15h /t48/tags/rel_0_6_beta/sw
127 + log status of A11 properly during interrupt routines
+ trigger counter on negative edge of T1 instead of positive edge
arniml 7299d 03h /t48/tags/rel_0_6_beta/sw
126 + specify hex file for external ROM on i8039 command line
+ support for no_dump_compare file in test cell
arniml 7299d 03h /t48/tags/rel_0_6_beta/sw
125 exclude from dump compare arniml 7299d 03h /t48/tags/rel_0_6_beta/sw
124 fix wrong handling of MB after return from interrupt arniml 7300d 01h /t48/tags/rel_0_6_beta/sw
123 support hex file for external ROM arniml 7300d 01h /t48/tags/rel_0_6_beta/sw
122 test MB after return from interrupt arniml 7300d 01h /t48/tags/rel_0_6_beta/sw
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"
arniml 7302d 18h /t48/tags/rel_0_6_beta/sw
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM
arniml 7343d 04h /t48/tags/rel_0_6_beta/sw
104 add white_box directory to test suite arniml 7347d 01h /t48/tags/rel_0_6_beta/sw
102 update for changes in address space of external memory arniml 7347d 01h /t48/tags/rel_0_6_beta/sw
99 initial check-in arniml 7347d 01h /t48/tags/rel_0_6_beta/sw

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