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[/] [t48/] [tags/] [rel_1_0/] [rtl/] [vhdl/] - Rev 187

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Rev Log message Author Age Path
187 Fix bug reports:
"Target address of JMP to Program Memory Bank 1 corrupted by interrupt"
"Return address of CALL to Program Memory Bank 1 corrupted by interrupt"
int_in_progress_o was active one cycle before int_pending_o is
asserted. this confused the mb multiplexer which determines the state of
the memory bank selection flag		 arniml 6875d 03h /t48/tags/rel_1_0/rtl/vhdl
183 fix missing assignment to outclock arniml 6881d 06h /t48/tags/rel_1_0/rtl/vhdl
180 introduce prefix 't48_' for wb_master entity and configuration arniml 6969d 14h /t48/tags/rel_1_0/rtl/vhdl
179 introduce prefix 't48_' for all packages, entities and configurations arniml 6969d 14h /t48/tags/rel_1_0/rtl/vhdl
178 Move latching of BUS to MSTATE2
-> sample BUS at the end of RD'		 arniml 6971d 02h /t48/tags/rel_1_0/rtl/vhdl
177 Implement db_dir_o glitch-safe arniml 6971d 02h /t48/tags/rel_1_0/rtl/vhdl
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6971d 02h /t48/tags/rel_1_0/rtl/vhdl
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6972d 05h /t48/tags/rel_1_0/rtl/vhdl
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7001d 01h /t48/tags/rel_1_0/rtl/vhdl
171 remove obsolete output stack_high_o arniml 7002d 02h /t48/tags/rel_1_0/rtl/vhdl
169 initial check-in arniml 7003d 13h /t48/tags/rel_1_0/rtl/vhdl
168 change address range of wb_master arniml 7003d 13h /t48/tags/rel_1_0/rtl/vhdl
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7003d 13h /t48/tags/rel_1_0/rtl/vhdl
166 assign default for state_s arniml 7005d 05h /t48/tags/rel_1_0/rtl/vhdl
165 add component wb_master.vhd arniml 7006d 04h /t48/tags/rel_1_0/rtl/vhdl
164 initial check-in arniml 7006d 04h /t48/tags/rel_1_0/rtl/vhdl
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7007d 04h /t48/tags/rel_1_0/rtl/vhdl
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7038d 08h /t48/tags/rel_1_0/rtl/vhdl
157 removed obsolete constant arniml 7159d 04h /t48/tags/rel_1_0/rtl/vhdl
156 added hierarchy t8039_notri arniml 7159d 04h /t48/tags/rel_1_0/rtl/vhdl

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