URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_0/] [sim/] - Rev 292

Rev	Log message	Author	Age	Path
292	New directory structure.	root	5588d 07h	/t48/tags/rel_1_0/sim
277	This commit was manufactured by cvs2svn to create tag 'rel_1_0'.		6400d 17h	/t48/tags/rel_1_0/sim
259	added t8243 core plus related testbenches	arniml	6558d 15h	/t48/tags/rel_1_0/sim
235	cleanup dependencies	arniml	6580d 16h	/t48/tags/rel_1_0/sim
232	update to new memory concept	arniml	6581d 15h	/t48/tags/rel_1_0/sim
223	obsoleted	arniml	6581d 16h	/t48/tags/rel_1_0/sim
218	simplifications	arniml	6668d 23h	/t48/tags/rel_1_0/sim
198	fix package dependencies	arniml	6813d 00h	/t48/tags/rel_1_0/sim
159	fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0	arniml	7145d 21h	/t48/tags/rel_1_0/sim
158	added hierarchies t8039_notri and t8048_notri	arniml	7145d 21h	/t48/tags/rel_1_0/sim
154	added t8039_notri hierarchy	arniml	7145d 21h	/t48/tags/rel_1_0/sim
151	added hierarchy t8048_notri and components package for t48 systems	arniml	7147d 09h	/t48/tags/rel_1_0/sim
116	adapt to GHDL 0.12 / gcc 3.4.0	arniml	7330d 20h	/t48/tags/rel_1_0/sim
112	update tb_behav_c0 for new ROM layout	arniml	7342d 05h	/t48/tags/rel_1_0/sim
93	add support for line coverage evaluation with gcov	arniml	7347d 01h	/t48/tags/rel_1_0/sim
84	add if_timing module	arniml	7367d 20h	/t48/tags/rel_1_0/sim
79	add if_timing module	arniml	7368d 00h	/t48/tags/rel_1_0/sim
77	move from std_logic_arith to numeric_std	arniml	7368d 17h	/t48/tags/rel_1_0/sim
76	initial check-in	arniml	7368d 21h	/t48/tags/rel_1_0/sim
75	remove obsolete design unit	arniml	7368d 21h	/t48/tags/rel_1_0/sim