OpenCores
URL https://opencores.org/ocsvn/t48/t48/trunk

Subversion Repositories t48

[/] [t48/] [tags/] [rel_1_1/] [sw/] [verif/] - Rev 238

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
238 initial check-in arniml 6594d 20h /t48/tags/rel_1_1/sw/verif
237 initial check-in arniml 6594d 21h /t48/tags/rel_1_1/sw/verif
236 initial check-in arniml 6594d 22h /t48/tags/rel_1_1/sw/verif
229 rework hex/simulation targets arniml 6597d 20h /t48/tags/rel_1_1/sw/verif
199 initial check-in arniml 6829d 00h /t48/tags/rel_1_1/sw/verif
194 initial check-in arniml 6830d 11h /t48/tags/rel_1_1/sw/verif
185 initial check-in arniml 6884d 00h /t48/tags/rel_1_1/sw/verif
184 initial check-in arniml 6884d 01h /t48/tags/rel_1_1/sw/verif
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 02h /t48/tags/rel_1_1/sw/verif
141 disable external memory to avoid conflicts with outl a, bus arniml 7201d 02h /t48/tags/rel_1_1/sw/verif
131 update arniml 7244d 21h /t48/tags/rel_1_1/sw/verif
130 initial check-in arniml 7244d 21h /t48/tags/rel_1_1/sw/verif
125 exclude from dump compare arniml 7314d 09h /t48/tags/rel_1_1/sw/verif
122 test MB after return from interrupt arniml 7315d 07h /t48/tags/rel_1_1/sw/verif
118 test MB/interrupt behaviour according to bug report
"Program Memory bank can be switched during interrupt"		 arniml 7318d 00h /t48/tags/rel_1_1/sw/verif
113 generate two ROM files based on address:
+ 0 - 2047 : 2k internal ROM
+ 2048 - 4095 : 2k external ROM		 arniml 7358d 10h /t48/tags/rel_1_1/sw/verif
102 update for changes in address space of external memory arniml 7362d 07h /t48/tags/rel_1_1/sw/verif
99 initial check-in arniml 7362d 07h /t48/tags/rel_1_1/sw/verif
97 initial check-in arniml 7362d 07h /t48/tags/rel_1_1/sw/verif
95 check counter inactivity arniml 7363d 05h /t48/tags/rel_1_1/sw/verif

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.