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[/] [t48/] [tags/] [rel_1_4] - Rev 177

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Rev Log message Author Age Path
177 Implement db_dir_o glitch-safe arniml 6974d 19h /t48/tags/rel_1_4
176 Use en_clk_i instead of xtal3_s for generation of external signals.
This is required when the core runs with full xtal clock instead
of xtal/3 (xtal_div_3_g = 0).		 arniml 6974d 19h /t48/tags/rel_1_4
175 add bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 22h /t48/tags/rel_1_4
174 fix bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 22h /t48/tags/rel_1_4
173 testcase for bug report
"MSB of Program Counter changed upon PC increment"		 arniml 6975d 22h /t48/tags/rel_1_4
172 save data from wishbone bus in register bank with wb_ack
necessary to hold data from peripheral/memory until it is read by T48		 arniml 7004d 19h /t48/tags/rel_1_4
171 remove obsolete output stack_high_o arniml 7005d 19h /t48/tags/rel_1_4
170 intermediate update arniml 7007d 02h /t48/tags/rel_1_4
169 initial check-in arniml 7007d 07h /t48/tags/rel_1_4
168 change address range of wb_master arniml 7007d 07h /t48/tags/rel_1_4
167 simplify address range:
- configuration range
- Wishbone range		 arniml 7007d 07h /t48/tags/rel_1_4
166 assign default for state_s arniml 7008d 23h /t48/tags/rel_1_4
165 add component wb_master.vhd arniml 7009d 22h /t48/tags/rel_1_4
164 initial check-in arniml 7009d 22h /t48/tags/rel_1_4
163 add bug
Wrong clock applied to T0		 arniml 7010d 21h /t48/tags/rel_1_4
162 Fix bug report:
"Wrong clock applied to T0"
t0_o is generated inside clock_ctrl with a separate flip-flop running
with xtal_i		 arniml 7010d 21h /t48/tags/rel_1_4
161 fix syntax problem that triggers an error with GHDL 0.18 arniml 7042d 01h /t48/tags/rel_1_4
160 add others to case statement arniml 7162d 22h /t48/tags/rel_1_4
159 fix dependencies for tb_t8048_behav_c0 and tb_t8039_behav_c0 arniml 7162d 22h /t48/tags/rel_1_4
158 added hierarchies t8039_notri and t8048_notri arniml 7162d 22h /t48/tags/rel_1_4

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