URL https://opencores.org/ocsvn/t80/t80/trunk

Subversion Repositories t80

[/] [t80/] [trunk/] [rtl/] - Rev 47

Rev	Log message	Author	Age	Path
47	New directory structure.	root	5571d 13h	/t80/trunk/rtl
46	Made some bugfixes	andreas	6859d 06h	/trunk/rtl
45	Fixed loopback break generation	jesus	7860d 08h	/trunk/rtl
44	Added some missing features and fixed baud rate generator	jesus	7860d 22h	/trunk/rtl
42	Fixed bus req/ack cycle	jesus	7869d 09h	/trunk/rtl
41	Removed UNISIM library	jesus	7869d 09h	/trunk/rtl
40	Cleanup	jesus	7869d 09h	/trunk/rtl
37	Changed to single register file	jesus	7897d 10h	/trunk/rtl
36	Added component declaration	jesus	7897d 10h	/trunk/rtl
35	Release 0242	jesus	7903d 22h	/trunk/rtl
34	Updated for ISE 5.1	jesus	7904d 03h	/trunk/rtl
29	Fixed (IX/IY+d) timing and added all GB op-codes	jesus	7922d 20h	/trunk/rtl
27	Xilinx SSRAM, initial release	jesus	7923d 21h	/trunk/rtl
26	Fixed instruction timing for POP and DJNZ	jesus	7937d 12h	/trunk/rtl
25	IX/IY timing and ADC/SBC fix	jesus	7938d 22h	/trunk/rtl
24	no message	jesus	7944d 19h	/trunk/rtl
23	Fixed T2Write	jesus	7944d 19h	/trunk/rtl
22	Added 8080 top level	jesus	7944d 19h	/trunk/rtl
20	Updated for new T80s generic	jesus	7949d 18h	/trunk/rtl
19	Initial version	jesus	7949d 18h	/trunk/rtl