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[/] [tinycpu/] [trunk/] - Rev 27

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Rev	Log message	Author	Age	Path
27	Added a few ALU opcodes and came across a weird propogation delay issue with my registerfile. As a workaround, I'm trying to use falling_edge instead of rising_edge. We shall see if I regret this later	earlz	4422d 13h	/tinycpu/trunk
26	Added extra check to make sure fetcher works properly after memory write	earlz	4422d 14h	/tinycpu/trunk
25	Wait for memory state now works as expected, and opcode `mov [reg], immd` works now	earlz	4422d 19h	/tinycpu/trunk
24	Good news, mov to IP actually works as expected!	earlz	4423d 12h	/tinycpu/trunk
23	Added top module for testing how our memory and cpu will work together. (hint: success) Messing around with a small timing issue in core	earlz	4423d 12h	/tinycpu/trunk
22	Added to process sensitivity list to avoid warning and added ELSE for IR so it doesn't generate a latch	earlz	4424d 04h	/tinycpu/trunk
21	The core_tb testbench finally passes. It probably doesn't synthesize, or even pass other testbenches, but it passes that one damn it.	earlz	4424d 05h	/tinycpu/trunk
20	fuck it. All sorts of broken, will try to fix it tomorrow	earlz	4425d 04h	/tinycpu/trunk
19	Got beginning of core/decoder for the CPU	earlz	4425d 06h	/tinycpu/trunk
18	Finished memory controller	earlz	4428d 16h	/tinycpu/trunk
17	Added fetch component for fetching from memory to instruction register Added additional testing for carryover to make sure it's correct	earlz	4429d 05h	/tinycpu/trunk
16	Renamed incdec to carryover (see design for why). carryover should be done, though may change the "straight through on disable" behavior to instead leaving it floating depending on how things go later with coding.	earlz	4432d 07h	/tinycpu/trunk
15	Added README, LICENSE, and the (so far not created) incdec component	earlz	4434d 05h	/tinycpu/trunk
14	Added ALU with all the operations we'll need. Synthesizes as well trivially	earlz	4434d 13h	/tinycpu/trunk
13	Forgot about the new library I added	earlz	4434d 16h	/tinycpu/trunk
12	registerfile has ports for every register now makefile now uses GHW file format for gtkwave instead of VCD	earlz	4434d 16h	/tinycpu/trunk
11	Finally, it synthesizes to BRAM.. Possibly need to fix how the DataOut syncs with WriteEnable and Address though if I plan to both read and write on the same clock edge	earlz	4438d 06h	/tinycpu/trunk
10	Just committing so I can keep this original that passes simulation, but still synthesizes to LUTs	earlz	4438d 06h	/tinycpu/trunk
9	Trying to add a byte-enable to the RAM. Used Xilinx's template for it, but ghdl won't pass the testbench	earlz	4438d 14h	/tinycpu/trunk
8	Added blockram for inferring actual block RAM. Now we need a memory controller, not a crappy memory emulation thing	earlz	4439d 13h	/tinycpu/trunk

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Subversion Repositories tinycpu

[/] [tinycpu/] [trunk/] - Rev 27

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