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[/] [tv80/] [trunk/] [rtl] - Rev 87

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Rev	Log message	Author	Age	Path
87	Added additional ifdef signals to remove unneede R (refresh) register	ghutchis	5408d 09h	/tv80/trunk/rtl
84	New directory structure.	root	5631d 21h	/tv80/trunk/rtl
83	Some fixes from Guy-- replace case with casex.	hharte	5705d 03h	/trunk/rtl
82	Clean up spacing	hharte	5714d 23h	/trunk/rtl
81	Initial version of TV80 Wishbone Wrapper	hharte	5714d 23h	/trunk/rtl
80	Misc. code clean-up on mcode to make code smaller and (hopefully) more readable.	ghutchis	6814d 11h	/trunk/rtl
78	Hajime Ishitani pointed out missing invert on cs_n signal	ghutchis	6857d 13h	/trunk/rtl
74	Changed default for T2Write to be 1, to match expected behavior for most users.	ghutchis	6968d 14h	/trunk/rtl
71	Ported UART from T80	ghutchis	7041d 13h	/trunk/rtl
65	Major restructuring of simple_gmii block. 1) Changed simple_gmii block to simple_gmii_core 2) Migrated RAM instances out of core into top level 3) Removed CPU interface logic and created CPU interface block using register generator 4) Changed status register to interrupt register and added interrupt logic	ghutchis	7100d 08h	/trunk/rtl
60	Added ifdef TV80_REFRESH, to remove refresh logic by default. Also ran untabify to remove tabs from source code.	ghutchis	7135d 12h	/trunk/rtl
58	Made TX path async Made TX clock input instead of output	ghutchis	7174d 23h	/trunk/rtl
52	Added simple GMII-like interface for testing	ghutchis	7177d 05h	/trunk/rtl
45	Added negedge version of top	ghutchis	7192d 09h	/trunk/rtl
33	Added missing IncDec controls to OUTI/OUTD instructions	ghutchis	7220d 06h	/trunk/rtl
24	tv80s.v	ghutchis	7248d 22h	/trunk/rtl
23	Completed conversion to one-hot encoding	ghutchis	7261d 13h	/trunk/rtl
22	Changed starting state for one-hot tstate	ghutchis	7261d 13h	/trunk/rtl
21	Replaced encoded states with one-hot	ghutchis	7262d 13h	/trunk/rtl
4	Removed obsolete top level	ghutchis	7390d 10h	/trunk/rtl

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Subversion Repositories tv80

[/] [tv80/] [trunk/] [rtl] - Rev 87

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