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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 63

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Rev	Log message	Author	Age	Path
63	Synplicity was having troubles with the comment.	mohor	8267d 23h	/uart16550/trunk/rtl/verilog
62	Bug that was entered in the last update fixed (rx state machine).	mohor	8268d 22h	/uart16550/trunk/rtl/verilog
61	overrun signal was moved to separate block because many sequential lsr reads were preventing data from being written to rx fifo. underrun signal was not used and was removed from the project.	mohor	8269d 16h	/uart16550/trunk/rtl/verilog
60	Things related to msr register changed. After THRE IRQ occurs, and one character is written to the transmit fifo, the detection of the THRE bit in the LSR is delayed for one character time.	mohor	8269d 21h	/uart16550/trunk/rtl/verilog
59	MSR register fixed.	mohor	8272d 18h	/uart16550/trunk/rtl/verilog
58	After reset modem status register MSR should be reset.	mohor	8272d 21h	/uart16550/trunk/rtl/verilog
57	timeout irq must be set regardless of the rda irq (rda irq does not reset the timeout counter).	mohor	8273d 21h	/uart16550/trunk/rtl/verilog
56	thre irq should be cleared only when being source of interrupt.	mohor	8273d 21h	/uart16550/trunk/rtl/verilog
55	some synthesis bugs fixed	gorban	8274d 09h	/uart16550/trunk/rtl/verilog
54	LSR status bit 0 was not cleared correctly in case of reseting the FCR (rx fifo).	mohor	8274d 22h	/uart16550/trunk/rtl/verilog
53	Scratch register define added.	mohor	8275d 22h	/uart16550/trunk/rtl/verilog
52	Scratch register added	gorban	8276d 11h	/uart16550/trunk/rtl/verilog
51	Igor fixed break condition bugs	gorban	8276d 11h	/uart16550/trunk/rtl/verilog
50	Bug in LSR[0] is fixed. All WISHBONE signals are now sampled, so another wait-state is introduced on all transfers.	gorban	8280d 16h	/uart16550/trunk/rtl/verilog
49	committed the debug interface file	gorban	8282d 10h	/uart16550/trunk/rtl/verilog
48	Updated specification documentation. Added full 32-bit data bus interface, now as default. Address is 5-bit wide in 32-bit data bus mode. Added wb_sel_i input to the core. It's used in the 32-bit mode. Added debug interface with two 32-bit read-only registers in 32-bit mode. Bits 5 and 6 of LSR are now only cleared on TX FIFO write. My small test bench is modified to work with 32-bit mode.	gorban	8283d 09h	/uart16550/trunk/rtl/verilog
47	Fixed: timeout and break didn't pay attention to current data format when counting time	gorban	8288d 11h	/uart16550/trunk/rtl/verilog
46	Fixed bug that prevented synthesis in uart_receiver.v	gorban	8289d 09h	/uart16550/trunk/rtl/verilog
45	Lots of fixes: Break condition wasn't handled correctly at all. LSR bits could lose their values. LSR value after reset was wrong. Timing of THRE interrupt signal corrected. LSR bit 0 timing corrected.	gorban	8290d 09h	/uart16550/trunk/rtl/verilog
44	fixed more typo bugs	gorban	8304d 09h	/uart16550/trunk/rtl/verilog

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[/] [uart16550/] [trunk/] [rtl/] [verilog/] - Rev 63

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