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Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] - Rev 30

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Rev Log message Author Age Path
30 MODIFIED: cosmetic changes on the SoftwareFolder.txt file aborga 4611d 23h /uart_fpga_slow_control
29 UPDATED: project documentation for the new software features aborga 4611d 23h /uart_fpga_slow_control
28 ADDED: software folder with python script (simple but stable) and .bat file to load RealTerm with parameters (extremely unstable) aborga 4612d 00h /uart_fpga_slow_control
27 MODIFIED: small description improvement aborga 4619d 00h /uart_fpga_slow_control
26 ADDED: screenshot of the simulation output with tb_uart_control.vhd (project tested with modelsim 6) aborga 4692d 21h /uart_fpga_slow_control
25 MODIFIED: small comment improvement aborga 4692d 23h /uart_fpga_slow_control
24 UPDATED: added folder testbenches with a generic tb_UART_control.vhd testbench aborga 4693d 00h /uart_fpga_slow_control
23 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4693d 01h /uart_fpga_slow_control
22 aborga 4693d 02h /uart_fpga_slow_control
21 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4693d 02h /uart_fpga_slow_control
20 MODIFIED: block diagram with new namings for uart din and dout aborga 4693d 02h /uart_fpga_slow_control
19 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4693d 02h /uart_fpga_slow_control
18 MODIFIED: removed unnecessary libraries aborga 4693d 23h /uart_fpga_slow_control
17 DELETED: useless package folder aborga 4694d 00h /uart_fpga_slow_control
16 MODIFIED: added

uart_rst_i : in std_logic;
uart_leds_o : out std_logic_vector(7 downto 0);

in the entity declaration
aborga 4694d 00h /uart_fpga_slow_control
15 UPDATED: email address aborga 4695d 23h /uart_fpga_slow_control
14 ADDED: backup of the project description aborga 4696d 15h /uart_fpga_slow_control
13 UDATED: simple documentation aborga 4696d 17h /uart_fpga_slow_control
12 ADDED: original documentation of the UART_16550 core by LeFevre aborga 4696d 17h /uart_fpga_slow_control
11 ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram
1) pdf format
2) Microsoft visio source file (sorry...)
aborga 4696d 17h /uart_fpga_slow_control

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