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Subversion Repositories uart_fpga_slow_control_migrated

[/] [uart_fpga_slow_control/] [trunk/] - Rev 27

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27 MODIFIED: small description improvement aborga 4647d 12h /uart_fpga_slow_control/trunk
26 ADDED: screenshot of the simulation output with tb_uart_control.vhd (project tested with modelsim 6) aborga 4721d 10h /uart_fpga_slow_control/trunk
25 MODIFIED: small comment improvement aborga 4721d 12h /uart_fpga_slow_control/trunk
24 UPDATED: added folder testbenches with a generic tb_UART_control.vhd testbench aborga 4721d 12h /uart_fpga_slow_control/trunk
23 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4721d 13h /uart_fpga_slow_control/trunk
22 aborga 4721d 14h /uart_fpga_slow_control/trunk
21 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4721d 14h /uart_fpga_slow_control/trunk
20 MODIFIED: block diagram with new namings for uart din and dout aborga 4721d 14h /uart_fpga_slow_control/trunk
19 MODIFIED:

renamed lantronix_input and lantronix_output (historical)
to uart_din and uart_dout for consistency

propagated also changes in all comments
aborga 4721d 15h /uart_fpga_slow_control/trunk
18 MODIFIED: removed unnecessary libraries aborga 4722d 11h /uart_fpga_slow_control/trunk
17 DELETED: useless package folder aborga 4722d 13h /uart_fpga_slow_control/trunk
16 MODIFIED: added

uart_rst_i : in std_logic;
uart_leds_o : out std_logic_vector(7 downto 0);

in the entity declaration
aborga 4722d 13h /uart_fpga_slow_control/trunk
15 UPDATED: email address aborga 4724d 12h /uart_fpga_slow_control/trunk
14 ADDED: backup of the project description aborga 4725d 04h /uart_fpga_slow_control/trunk
13 UDATED: simple documentation aborga 4725d 06h /uart_fpga_slow_control/trunk
12 ADDED: original documentation of the UART_16550 core by LeFevre aborga 4725d 06h /uart_fpga_slow_control/trunk
11 ADDED: Block diagram of the UART_FPGA_slow_control_main_diagram
1) pdf format
2) Microsoft visio source file (sorry...)
aborga 4725d 06h /uart_fpga_slow_control/trunk
10 MODIFIED: added further description and examples aborga 4725d 12h /uart_fpga_slow_control/trunk
9 ADDED: HowToSVN.txt to handle repositories with windows Tortoise SVN aborga 4725d 13h /uart_fpga_slow_control/trunk
8 ADDED: some more documentation

1) screenshot of a full read and write sequence with questasim
2) example hex commands to be sent via RealTerm
aborga 4725d 13h /uart_fpga_slow_control/trunk

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